search for: load11

...e an IR example of the case I'm interested in. Consider define void @"julia_transform_bvn_derivs_hessian!"(double* %data, double* %data2, double *%data3, double *%out) { %element11 = getelementptr inbounds double, double* %data, i32 1 %load10 = load double, double* %data %load11 = load double, double* %element11 %element21 = getelementptr inbounds double, double* %data2, i32 1 %element22 = getelementptr inbounds double, double* %data2, i32 2 %element23 = getelementptr inbounds double, double* %data2, i32 3 %load20 = load double, double* %data2 %load21...

There was some discussion of this on the llvm-commits list, but I wanted to raise the topic for discussion here. The background of the -commits discussion was that r296863 added the ability to sort memory access when the SLP vectorizer reached a load (the SLP vectorizer starts at a store or some other sink, and tries to go up the tree vectorizing as it goes along - if the input is in a different

...d <4 x i8>* %7, align 1 > 2794 %8 = zext <4 x i8> %wide.load to <4 x i32> > 2795 %9 = zext <4 x i8> %wide.load10 to <4 x i32> > 2796 %10 = getelementptr inbounds i8* %pix2, i64 %index > 2797 %11 = bitcast i8* %10 to <4 x i8>* > 2798 %wide.load11 = load <4 x i8>* %11, align 1 > 2799 %.sum20 = or i64 %index, 4 > 2800 %12 = getelementptr i8* %pix2, i64 %.sum20 > 2801 %13 = bitcast i8* %12 to <4 x i8>* > 2802 %wide.load12 = load <4 x i8>* %13, align 1 > 2803 %14 = zext <4 x i8> %wide.load11 to &...

...;* %7, align 1 > > 2794 %8 = zext <4 x i8> %wide.load to <4 x i32> > > 2795 %9 = zext <4 x i8> %wide.load10 to <4 x i32> > > 2796 %10 = getelementptr inbounds i8* %pix2, i64 %index > > 2797 %11 = bitcast i8* %10 to <4 x i8>* > > 2798 %wide.load11 = load <4 x i8>* %11, align 1 > > 2799 %.sum20 = or i64 %index, 4 > > 2800 %12 = getelementptr i8* %pix2, i64 %.sum20 > > 2801 %13 = bitcast i8* %12 to <4 x i8>* > > 2802 %wide.load12 = load <4 x i8>* %13, align 1 > > 2803 %14 = zext <4 x i8> %w...

----- Original Message ----- > From: "Renato Golin" <renato.golin at linaro.org> > To: "Dibyendu Das" <Dibyendu.Das at amd.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Tuesday, November 4, 2014 5:23:30 AM > Subject: Re: [LLVMdev] supporting SAD in loop vectorizer > > On 4 November 2014 11:06, Das, Dibyendu <Dibyendu.Das at amd.com> wrote:

...00ef000 at 0x0780c000: load8b ALLOC READONLY > CODE > ??? 0x7f73f0103000->0x7f73f0103000 at 0x0780c000: load9 ALLOC READONLY > ??? 0x7f73f0302000->0x7f73f0303000 at 0x0780c000: load10 ALLOC LOAD > READONLY HAS_CONTENTS > ??? 0x7f73f0303000->0x7f73f0304000 at 0x0780d000: load11 ALLOC LOAD > HAS_CONTENTS > ??? 0x7f73f0304000->0x7f73f0305000 at 0x0780e000: load12a ALLOC LOAD > READONLY CODE HAS_CONTENTS > ??? 0x7f73f0305000->0x7f73f0305000 at 0x0780f000: load12b ALLOC > READONLY CODE > ??? 0x7f73f030c000->0x7f73f030c000 at 0x0780f000: load13...

On Wed, Jan 24, 2018 at 18:55:47 +0100, Thomas Robers wrote: > Am 23.01.2018 um 20:07 schrieb Josef 'Jeff' Sipek: > > On Tue, Jan 23, 2018 at 14:03:27 -0500, Josef 'Jeff' Sipek wrote: > > > On Tue, Jan 23, 2018 at 18:21:38 +0100, Thomas Robers wrote: ... > > > 1. Do you have any idea what the imap process was doing at the time of the > > >

...x7f73f00ef000->0x7f73f00ef000 at 0x0780c000: load8b ALLOC READONLY CODE 0x7f73f0103000->0x7f73f0103000 at 0x0780c000: load9 ALLOC READONLY 0x7f73f0302000->0x7f73f0303000 at 0x0780c000: load10 ALLOC LOAD READONLY HAS_CONTENTS 0x7f73f0303000->0x7f73f0304000 at 0x0780d000: load11 ALLOC LOAD HAS_CONTENTS 0x7f73f0304000->0x7f73f0305000 at 0x0780e000: load12a ALLOC LOAD READONLY CODE HAS_CONTENTS 0x7f73f0305000->0x7f73f0305000 at 0x0780f000: load12b ALLOC READONLY CODE 0x7f73f030c000->0x7f73f030c000 at 0x0780f000: load13 ALLOC READONLY 0x7f73f05...