Displaying 11 results from an estimated 11 matches for "llvmdevelopersmeetingbay2016".
2016 Nov 15
2
CTMark - regular LLVM and CLANG compile-time tracking
...an.php?page=article&item=llvm-clang-39&num=4 <http://www.phoronix.com/scan.php?page=article&item=llvm-clang-39&num=4>. At the LLVM Developer Meeting Michael showed double digit compile-time increases in clang 3.7 and 3.8 in Os/O3 and O0 in his Loop Passes presentation (https://llvmdevelopersmeetingbay2016.sched.org/event/8Z0B/loop-passes-adding-new-features-while-reducing-technical-debt <https://llvmdevelopersmeetingbay2016.sched.org/event/8Z0B/loop-passes-adding-new-features-while-reducing-technical-debt>):
The selection of 10 tests out of the LLVM tests invites criticism. The motivation h...
2016 Oct 14
5
BoF: Shipping Software as LLVM IR (@Upcoming Dev Mtg)
Hi LLVM’ers!
We are hosting a BoF at this year's Dev Meeting on a subject we hope will
be of interest to some (many?) of you:
shipping software (entirely) as LLVM IR.
You can find our proposal in the meeting schedule online:
https://llvmdevelopersmeetingbay2016.sched.org/event/8Yzq/shipping-software-as-llvm-ir
The BoF is scheduled to last 45 minutes, which will go by very quickly!
To make the best use of the time, we'd like to get a head-start on some of
the discussions,
and get a feel for what topics people are most interested in discussing.
To star...
2016 Nov 17
4
CTMark - regular LLVM and CLANG compile-time tracking
...an.php?page=article&item=llvm-clang-39&num=4 <http://www.phoronix.com/scan.php?page=article&item=llvm-clang-39&num=4>. At the LLVM Developer Meeting Michael showed double digit compile-time increases in clang 3.7 and 3.8 in Os/O3 and O0 in his Loop Passes presentation (https://llvmdevelopersmeetingbay2016.sched.org/event/8Z0B/loop-passes-adding-new-features-while-reducing-technical-debt <https://llvmdevelopersmeetingbay2016.sched.org/event/8Z0B/loop-passes-adding-new-features-while-reducing-technical-debt>):
>> <PastedGraphic-3.png>
>>
>>
>> The selection of 10...
2016 Dec 12
0
LLVM possible projects
...t be able to shed some light on the open project issue.
Cheers,
Johannes
[0] http://compilers.cs.uni-saarland.de/teaching/cc/2015/slides/llvm-ir.pdf
[1] http://compilers.cs.uni-saarland.de/teaching/cc/2015/
[2] http://compilers.cs.uni-saarland.de/teaching/cc/2015/example-llvm-ir.tar
[3] https://llvmdevelopersmeetingbay2016.sched.com/event/8Yzs/raising-next-generation-of-llvm-developers
[4] http://llvm.org/OpenProjects.html
On 12/10, vivek pandya via llvm-dev wrote:
> > Hello,
> > Presently my research is focused on compiler and i found LLVM great tool to
> > work with. I want to familiarize it at u...
2016 Oct 17
3
BoF: Shipping Software as LLVM IR (@Upcoming Dev Mtg)
...vm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
Hi LLVM’ers!
We are hosting a BoF at this year's Dev Meeting on a subject we hope will be of interest to some (many?) of you:
shipping software (entirely) as LLVM IR.
You can find our proposal in the meeting schedule online:
https://llvmdevelopersmeetingbay2016.sched.org/event/8Yzq/shipping-software-as-llvm-ir<https://urldefense.proofpoint.com/v2/url?u=https-3A__llvmdevelopersmeetingbay2016.sched.org_event_8Yzq_shipping-2Dsoftware-2Das-2Dllvm-2Dir&d=DQMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=b7uK7dJM4Fx7J_ehsuohEdD-6NdkoLyTwBFfHX-XKcc&m=2ty5V_F2...
2016 Oct 17
0
BoF: Shipping Software as LLVM IR (@Upcoming Dev Mtg)
...>> We are hosting a BoF at this year's Dev Meeting on a subject we hope will be of interest to some (many?) of you:
>>> shipping software (entirely) as LLVM IR.
>>>
>>> You can find our proposal in the meeting schedule online:
>>>
>>> https://llvmdevelopersmeetingbay2016.sched.org/event/8Yzq/shipping-software-as-llvm-ir <https://urldefense.proofpoint.com/v2/url?u=https-3A__llvmdevelopersmeetingbay2016.sched.org_event_8Yzq_shipping-2Dsoftware-2Das-2Dllvm-2Dir&d=DQMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=b7uK7dJM4Fx7J_ehsuohEdD-6NdkoLyTwBFfHX-XKcc&m=2ty5V_F...
2016 Oct 27
1
BoF: Shipping Software as LLVM IR (@Upcoming Dev Mtg)
...ing a BoF at this year's Dev Meeting on a subject we hope will be of interest to some (many?) of you:
>>>> shipping software (entirely) as LLVM IR.
>>>>
>>>> You can find our proposal in the meeting schedule online:
>>>>
>>>> https://llvmdevelopersmeetingbay2016.sched.org/event/8Yzq/shipping-software-as-llvm-ir <https://urldefense.proofpoint.com/v2/url?u=https-3A__llvmdevelopersmeetingbay2016.sched.org_event_8Yzq_shipping-2Dsoftware-2Das-2Dllvm-2Dir&d=DQMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=b7uK7dJM4Fx7J_ehsuohEdD-6NdkoLyTwBFfHX-XKcc&m=2ty5V_F...
2016 Dec 10
3
LLVM possible projects
> Hello,
> Presently my research is focused on compiler and i found LLVM great tool to
> work with. I want to familiarize it at undergraduate level.
>
> Hi Hameeza,
I have face similar situation before and I would suggest you to read some
books/ blogs available on Internet for LLVM.
I think the best way to understand LLVM is by playing with it.
Then you should try doing some
2016 Nov 17
4
RFC: Insertion of nops for performance stability
...oded Stream Buffer) Thrashing.
DSB is a cache for uops that have been decoded. It is limited to 3 ways per 32B window; 4 or more ways will cause a performance degradation. This can be avoided by aligning with nops. See Zia Ansari's presentation for more information: http://schd.ws/hosted_files/llvmdevelopersmeetingbay2016/d9/LLVM-Conference-US-2016-Code-Alignment.pdf
2. Two or more branches with the same target in a single instruction window may cause poor branch prediction.
Our recommendation to programmers is to try and keep 2 branches out of the same 16B chunk if they both go to the same target. From the m...
2016 Nov 20
3
RFC: Insertion of nops for performance stability
...oded Stream Buffer) Thrashing.
DSB is a cache for uops that have been decoded. It is limited to 3 ways per 32B window; 4 or more ways will cause a performance degradation. This can be avoided by aligning with nops. See Zia Ansari's presentation for more information: http://schd.ws/hosted_files/llvmdevelopersmeetingbay2016/d9/LLVM-Conference-US-2016-Code-Alignment.pdf
2. Two or more branches with the same target in a single instruction window may cause poor branch prediction.
Our recommendation to programmers is to try and keep 2 branches out of the same 16B chunk if they both go to the same target. From the m...
2016 Nov 21
2
RFC: Insertion of nops for performance stability
...oded Stream Buffer) Thrashing.
DSB is a cache for uops that have been decoded. It is limited to 3 ways per 32B window; 4 or more ways will cause a performance degradation. This can be avoided by aligning with nops. See Zia Ansari's presentation for more information: http://schd.ws/hosted_files/llvmdevelopersmeetingbay2016/d9/LLVM-Conference-US-2016-Code-Alignment.pdf
2. Two or more branches with the same target in a single instruction window may cause poor branch prediction.
Our recommendation to programmers is to try and keep 2 branches out of the same 16B chunk if they both go to the same target. From the m...