Displaying 7 results from an estimated 7 matches for "llvm38nov2016".
2016 Jan 07
3
BPF backend with vector operations - some strange error
...;;
in order to support vector for example, ADD operations, I get the following error when
building llc:
JEQ_ri: (BPFbrcc i64:i64:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
(imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPFInstrInfo.td:131:1: error: In JEQ_ri: Could
not infer all types in pattern!
defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
The error is a bit cryptic - basically it seems that we can have 2 different value...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
...example, ADD operations, I get the following error when
>> building llc:
>> JEQ_ri: (BPFbrcc i64:i64:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
>> (imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
>> Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
>> ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPFInstrInfo.td:131:1: error: In JEQ_ri: Could
>> not infer all types in pattern!
>> defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
>>
>>
>> The error is a bit cryptic - basi...
2016 Apr 29
3
Assert in TargetLoweringBase.cpp
This post is related to the following post
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html
I'm still trying to compile a library with clang. But now I'm getting as
assert in
lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT
llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT)
const: Assertion `!VT.isVector() && "No default
2016 Jan 25
2
Instruction selection gives "LLVM ERROR: Cannot select"
Hello.
I'm writing a back end for a RISC processor (similar to BPF) with a large SIMD unit.
I tried in the last days to make llc compile to SIMD code the following LLVM program:
define i32 @foo(i32* %A, i32* %B, i32* %C, i32 %N) #0 {
entry: ;vector.body: ; preds = %vector.body, %vector.body.preheader.split.split
%0 = getelementptr inbounds i32, i32* %A, i64 0 ; i64 %index ; Alex: I
2016 Feb 04
2
llc gives Segmentation fault at instruction selection [was Re: Instruction selection gives "LLVM ERROR: Cannot select"]
...vector store from Mips) during selection gets modified during the
combine or lowering (I guess) and when instruction selection reaches the store it has one
input that is NULL (hence the segfault). More exactly, if we use GDB we see that at the
i-sel of the store we have:
┌──/home/asusu/LLVM/llvm38Nov2016/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
│858 /// Initialize the operands list of this with N operands.│
│859 void InitOperands(SDUse *Ops, const SDValue *Vals, unsigned N) {│
│860 for (unsigned i = 0; i != N; ++i) {│
│861 Ops[i].setUser(this);│...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure:
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...undef:i64, undef:i64, undef:i64,
undef:i64...
Split node result: t128: v2i64 = BUILD_VECTOR undef:i64, undef:i64
Split node operand: t122: v128i16,ch = masked_gather<LD128[<unknown>](align=256)> t0,
t130, t193, TargetConstant:i64<0>, t121
llc:
/home/asusu/LLVM/llvm38Nov2016/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6804:
llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&,
llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <=
MMO->getSize() && "Size mismatch!"' failed....