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Hi, We are experimenting directly generating vectorized LLVM IR (using <8 x float> kind of types), then compiling the code to SSE on a 64 bits machine. Right now the equivalent code in scalar mode sill outperform the SSE one. What is the quality of the SSE support in X86 LLVL backend? Are they any specific things to be aware of to improve the speed? Thanks Stéphane Letz

...converted in 0x3FE99999A0000000 by LLVM (looking at textual generated IR) but the following tool: http://babbage.cs.qc.edu/IEEE-754/Decimal.html gives: 0x3FE999999999999A instead and this value cannot be read back by "llc"... Am I the only one to need to generate constants float in LLVL IR ? Stéphane Letz

Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't

...Hi, > > We are experimenting directly generating vectorized LLVM IR (using <8 x float> kind of types), then compiling the code to SSE on a 64 bits machine. Right now the equivalent code in scalar mode sill outperform the SSE one. > > What is the quality of the SSE support in X86 LLVL backend? Are they any specific things to be aware of to improve the speed? > > Thanks > > Stéphane Letz > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://list...