Displaying 4 results from an estimated 4 matches for "llbb".
2015 Apr 28
9
[LLVMdev] RFC: Machine Level IR text-based serialization format
...r label %10
; <label>:10 ; preds = %0, %4
%11 = phi i32 [ %9, %4 ], [ 1, %0 ]
ret i32 %11
}
...
---
number: 0
name: fact
alignment: 4
regInfo:
....
frameInfo:
....
body:
- bb: 0
llbb: '%0'
successors: [ 'bb#2', 'bb#1' ]
liveIns: [ '%edi' ]
instructions:
- 'push64r undef %rax, %rsp, %rsp'
- 'mov32mr %rsp, 1, %noreg, 4, %noreg, %edi'
- ....
....
- bb:...
2015 Apr 28
3
[LLVMdev] RFC: Machine Level IR text-based serialization format
...>
> ret i32 %11
>
> }
>
>
> ...
>
> ---
>
> number: 0
>
> name: fact
>
> alignment: 4
>
> regInfo:
>
> ....
>
> frameInfo:
>
> ....
>
> body:
>
> - bb: 0
>
> llbb: '%0'
>
> successors: [ 'bb#2', 'bb#1' ]
>
> liveIns: [ '%edi' ]
>
> instructions:
>
> - 'push64r undef %rax, %rsp, %rsp'
>
> - 'mov32mr %rsp, 1, %noreg, 4, %noreg, %edi'
&g...
2015 Apr 29
3
[LLVMdev] RFC: Machine Level IR text-based serialization format
...fact
>>>
>>> alignment: 4
>>>
>>> regInfo:
>>>
>>> ....
>>>
>>> frameInfo:
>>>
>>> ....
>>>
>>> body:
>>>
>>> - bb: 0
>>>
>>> llbb: '%0'
>>>
>>> successors: [ 'bb#2', 'bb#1' ]
>>>
>>> liveIns: [ '%edi' ]
>>>
>>> instructions:
>>>
>>> - 'push64r undef %rax, %rsp, %rsp'
>>...
2015 Apr 28
2
[LLVMdev] RFC: Machine Level IR text-based serialization format
...>
> ret i32 %11
>
> }
>
>
> ...
>
> ---
>
> number: 0
>
> name: fact
>
> alignment: 4
>
> regInfo:
>
> ....
>
> frameInfo:
>
> ....
>
> body:
>
> - bb: 0
>
> llbb: '%0'
>
> successors: [ 'bb#2', 'bb#1' ]
>
> liveIns: [ '%edi' ]
>
> instructions:
>
> - 'push64r undef %rax, %rsp, %rsp'
>
> - 'mov32mr %rsp, 1, %noreg, 4, %noreg, %edi'
&g...