search for: livevars

I'm trying to write two LLVM passes, one of which uses the results of the other. The first is LiveVars and the second is RemoveUseless. In the RemoveUseless class I have: virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<LiveVars>(); } This compiles fine, but when I try to run it I get an error: Pass class not registered! The error goes away if I...

...are loading successfully. > > 2) Do both passes have a static <Passname>::ID variable defined in their > respective .cpp files? > > Yes. I also tried initializing them with different values. Just to be paranoid: each pass is using its own ID varibles, correct? > > 3) Is LiveVars an analysis pass? Does it say that it preserves all > other passes in its getAnalysisUsage() method? If not, you could have a > dependency chain that never gets resolved. > > I inserted AU.setPreservesAll() in getAnalysisUsage of the first pass I assume the first pass is an analysis p...

...ite these passes so that they can be rerun as needed? Is all but LiveIntervals > ok with this as of now? So the good news is that we are slowly moving towards a similar design. The bad news is that we are *slowly* moving... Currently, the register allocator super-pass contains these passes: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - RegAlloc Currently, LiveVars requires SSA form, and LiveIntervals only works with simple multi-defs as produced by PhiElim and TwoAddr. That means the pass order is fixed. The plan is to teach PhiELim and TwoAddr how to update LiveIntervals so it...

Hi (Jakob), in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed can be reused by another MI - these live ranges do

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch? Normally, it should...

On Dec 7, 2007, at 1:43 AM, Wojciech Matyjewicz wrote: > Recently, I was looking into the bug #1227. I wanted to check if > reordering optimization passes could solve it. To start with, I > tried to > reproduce the output of llvm-g++ -O3 using the combination of llvm-g++ > -O0 and opt with the appropriate passes. However, I was unable to. I > use > SVN versions of llvm and

Say I want to find all LLVM Value*-es that a live on exit from a basic block. What's the best way? - The 'LiveRange', 'LiveVariables' and 'LiveIntervals' classes seem to be tied to register allocation. - The ./lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.h file seem to provide what I need, but it's no a public header. - Volodya

Thanks for reviving this. I completely forgot the details but I resolved this problem. Looking though the code, seems I forked RewriteStatepointsForGC pass, and change it to adding 'gc-livevars' bundle to the call/invoke inst after finding the livevars, instead of changing it to StatepointCall intrinsic. On Wed, Nov 14, 2018 at 11:48 AM Philip Reames <listmail at philipreames.com> wrote: > Returning to an ancient thread. Sorry for the prolonged lack of response. > >...

Hi, Recently, I was looking into the bug #1227. I wanted to check if reordering optimization passes could solve it. To start with, I tried to reproduce the output of llvm-g++ -O3 using the combination of llvm-g++ -O0 and opt with the appropriate passes. However, I was unable to. I use SVN versions of llvm and llvm-gcc-4.2. First, I compile example.cpp (attached; taken from the bug #1227) with: $

Thanks for the detailed response. On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote: > Right. Evan is currently focusing on getting the late stages of > the code > generator (e.g. livevars) to be able to understand arbitrary machine > instrs in the face of physreg subregs. This lays the groundwork for > handling vreg subregs, but won't solve it directly. Is the work Evan doing a prerequisite for supporting vreg subregs? Is there a PR for the feature Evan is working on? &...

I have seen INITIALIZE_PASS(LiveVariables, "livevars", "Live Variable Analysis", false, false); in the llvm/lib/codegen/LiveVariables.cpp, where LiveVariables is a subclass of MachineFunctionPass, and #define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \ static RegisterPass<passName> passName ## _info(arg, name, cfg, an...

...achableblockelim -codegenprepare -stack-protector -preverify -domtree -verify -loops -branch-prob -expand-isel-pseudos -tailduplication -opt-phis -localstackalloc -dead-mi-elimination -machinedomtree -machine-loops -machinelicm -machine-cse -machine-sink -peephole-opts -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -processimpdefs -slotindexes -liveintervals -livedebugvars -simple-register-coalescing -calcspillweights -livestacks -virtregmap -edge-bundles -spill-code-placement -stack-slot-coloring -machinelicm -edge-bundles -prologepilog -branch-folder -tailduplica...

On Jul 4, 2012, at 5:35 AM, Philipp Brüschweiler <blei42 at gmail.com> wrote: > Hi everyone > > I'm hitting an assertion in PHIElimination.cpp:375. > > "Terminator instructions cannot use virtual registers unless" > "they are the first terminator in a block!" > > I was looking at the code around that location a bit and have not found > a

...ree -slotindexes -stack-coloring -localstackalloc -dead-mi-elimination -machinedomtree -machine-loops -machine-trace-metrics -early-ifcvt -machinelicm -machine-cse -machinepostdomtree -machine-block-freq -machine-sink -peephole-opts -dead-mi-elimination -processimpdefs -unreachable-mbb-elimination -livevars -machinedomtree -machine-loops -phi-node-elimination -twoaddressinstruction -slotindexes -liveintervals -simple-register-coalescing -misched -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -virtregrewriter -stack-slot-coloring -machineli...

On Apr 23, 2007, at 4:07 PM, Christopher Lamb wrote: > Thanks for the detailed response. > > On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote: > >> Right. Evan is currently focusing on getting the late stages of >> the code >> generator (e.g. livevars) to be able to understand arbitrary machine >> instrs in the face of physreg subregs. This lays the groundwork for >> handling vreg subregs, but won't solve it directly. > > Is the work Evan doing a prerequisite for supporting vreg subregs? Sort of. vreg subregs work can sta...

...degenprepare -stack-protector -preverify > -domtree -verify -loops -branch-prob -expand-isel-pseudos > -tailduplication -opt-phis -localstackalloc -dead-mi-elimination > -machinedomtree -machine-loops -machinelicm -machine-cse -machine-sink > -peephole-opts -unreachable-mbb-elimination -livevars > -phi-node-elimination -twoaddressinstruction -processimpdefs > -slotindexes -liveintervals -livedebugvars -simple-register-coalescing > -calcspillweights -livestacks -virtregmap -edge-bundles > -spill-code-placement -stack-slot-coloring -machinelicm -edge-bundles > -prologepilog -b...

...ferencing a subvalue of > the produced value (perhaps a subclass of SDOperand?). This would > allow the register allocator to try to use the sub/super register > sets to perform the instert/extract. Right. Evan is currently focusing on getting the late stages of the code generator (e.g. livevars) to be able to understand arbitrary machine instrs in the face of physreg subregs. This lays the groundwork for handling vreg subregs, but won't solve it directly. > Is any of this kind of work planned? The addition of those > MRegisterInfo functions has me curious... This is on our...

Hi everyone I'm hitting an assertion in PHIElimination.cpp:375. "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!" I was looking at the code around that location a bit and have not found a reason why this assertion has to hold, except for a comment: // In our final twist, we have to decide which instruction

On Wed, 11 May 2005, Alkis Evlogimenos wrote: > On Wed, 2005-05-11 at 13:17 -0500, Chris Lattner wrote: >> On Wed, 11 May 2005, Vladimir Prus wrote: >>> Say I want to find all LLVM Value*-es that a live on exit from a basic block. >>> What's the best way? >>> >>> - The 'LiveRange', 'LiveVariables' and 'LiveIntervals' classes

On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote: > On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > >> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: >> >>> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>>> How can one let the back end know how to insert and extract >>>> elements of >>>> a vector through sub-register