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...nderstand it, register allocators are implemented as > >> MachineFunctionPasses. Does a MachineFunction object contain all > >> information needed for a (classic) allocator? > > > > It has the instructions, operands and dependencies among them. There's > > a LiveInvervalAnalysis pass which you'll probably also need. That should > > be enough to get going. > > I was able to set up my own allocator that uses LiveIntervals and it is > currently printing out something that might become a conflict graph ;). > Would be nice if there was some documentation...

...>> - As far as I understand it, register allocators are implemented as >> MachineFunctionPasses. Does a MachineFunction object contain all >> information needed for a (classic) allocator? > > It has the instructions, operands and dependencies among them. There's > a LiveInvervalAnalysis pass which you'll probably also need. That should > be enough to get going. I was able to set up my own allocator that uses LiveIntervals and it is currently printing out something that might become a conflict graph ;). Would be nice if there was some documentation about how to get all th...

...anding the broad picture. > - As far as I understand it, register allocators are implemented as > MachineFunctionPasses. Does a MachineFunction object contain all > information needed for a (classic) allocator? It has the instructions, operands and dependencies among them. There's a LiveInvervalAnalysis pass which you'll probably also need. That should be enough to get going. > - Is there already a pass that prints interference graph (Chaitin et al. > 1981) or something similar like opt -view-cfg prints a CFG? If not, is > it even possible with the current LLVM infrastructure? The...

Hello, I want learn more about register allocation and do some analysis for a current research project. After reading some papers (eg. Chaitin, Briggs) I think its time to get my hands dirty :). First I plan to (re)implement some of the classic approaches to get familiar with the framework. At the beginning the following questions came up: - Is there some documentation about register allocation