Displaying 3 results from an estimated 3 matches for "liveinmbbs".
2009 Jan 13
2
[LLVMdev] Possible bug in the ARM backend?
...-ins for each MBB, just like LinearScan
does it at the end of the RALinScan::linearScan() function???
E.g. like this:
// Add live-ins to every BB except for entry. Also perform trivial coalescing.
MachineFunction::iterator EntryMBB = mf_->begin();
SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
LiveInterval &cur = *i->second;
unsigned Reg = 0;
bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
if (isPhys)
Reg = cur.reg;
else if (vrm_->isAssignedReg(cur.reg...
2009 Jan 13
0
[LLVMdev] Possible bug in the ARM backend?
On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com
> wrote:
> 2009/1/13 Evan Cheng <echeng at apple.com>:
>>
>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote:
>>
>>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1:
>>> Predecessors according to CFG: 0x8fdac90 (#0)
>>> %R0<def> = MOVi 0, 14, %reg0,
2009 Jan 13
2
[LLVMdev] Possible bug in the ARM backend?
2009/1/13 Evan Cheng <echeng at apple.com>:
>
> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote:
>
>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1:
>> Predecessors according to CFG: 0x8fdac90 (#0)
>> %R0<def> = MOVi 0, 14, %reg0, %reg0
>> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4)
>> [0x8fc2d68 + 0]