search for: listscheduletopdown

Hi All, While reading SchedulePostRATDList::ListScheduleTopDown() [1], I find SchedulingPriorityQueue::dump has an empty implementation. Therefore, the following debug dump basically outputs nothing. DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this)); Not sure why we want this. Is it intended? [1] http://llvm.or...

...10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9 To be scheduled first (!). Right there after 7 clang 0x000000000226aece llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378 8 clang 0x0000000001c2574f llvm::VLIWMachineScheduler::listScheduleTopDown() + 595 9 clang 0x0000000001c24cd5 llvm::VLIWMachineScheduler::schedule() + 505 It does not seem to happen on the trunk. My question is - Does anyone recognizes the issue, and what patch(es) do I need to address it. Since my release is based on 3.1, I have to cherry pick them... Any le...

..., 0; mem:LD4[%stack.0.in] > IntRegs:%vreg10,%vreg9 > > To be scheduled first (!). Right there after > > 7 clang 0x000000000226aece > llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378 > 8 clang 0x0000000001c2574f > llvm::VLIWMachineScheduler::listScheduleTopDown() + 595 > 9 clang 0x0000000001c24cd5 llvm::VLIWMachineScheduler::schedule() > + 505 > > It does not seem to happen on the trunk. > > My question is - Does anyone recognizes the issue, and what patch(es) do I > need to address it. Since my release is based on 3.1, I...

On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Looking at VLIWPacketizerList::PacketizeMIs, it seems like the > instructions are first scheduled (via some external scheme?), and then > packetized 'in order'. Is that correct? Anshu? > In the PowerPC grouping scheme, resources are assigned on a group > basis (by the instruction dispatching

...processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the argument Stalls = 0. This is no surprise since in PostRASchedulerList.cpp we have only one call to it, in method SchedulePostRATDList::ListScheduleTopDown(): ScheduleHazardRecognizer::HazardType HT = HazardRec->getHazardType(CurSUnit, 0/*no stalls*/); Let me state what I have added to my back end to enable scheduling with hazards: - inspiring from lib/Target/PowerPC/PPCHazardRecognizers.h, I have created a class [Targ...

...ntRegs:%vreg10,%vreg9 > > > > To be scheduled first (!). Right there after > > > > 7 clang 0x000000000226aece > > llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378 > > 8 clang 0x0000000001c2574f > > llvm::VLIWMachineScheduler::listScheduleTopDown() + 595 > > 9 clang 0x0000000001c24cd5 > llvm::VLIWMachineScheduler::schedule() > > + 505 > > > > It does not seem to happen on the trunk. > > > > My question is - Does anyone recognizes the issue, and what patch(es) > > do I need to address i...

On Mon, 11 Jun 2012 10:48:18 -0700 Andrew Trick <atrick at apple.com> wrote: > On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > I'm considering writing more-detailed itineraries for some PowerPC > > CPUs that use the 'traditional' instruction grouping scheme. In > > essence, this means that multiple instructions will stall

...; > > > To be scheduled first (!). Right there after > > > > > > 7 clang 0x000000000226aece > > > llvm::LiveIntervals::handleMove(llvm::MachineInstr*) + 378 > > > 8 clang 0x0000000001c2574f > > > llvm::VLIWMachineScheduler::listScheduleTopDown() + 595 > > > 9 clang 0x0000000001c24cd5 > > llvm::VLIWMachineScheduler::schedule() > > > + 505 > > > > > > It does not seem to happen on the trunk. > > > > > > My question is - Does anyone recognizes the issue, and what > &g...

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure: