Displaying 2 results from an estimated 2 matches for "lirximmx16".
2012 Oct 19
2
[LLVMdev] interesting minor llvm optimizer flaw
...aced in a simple
immediate field.
That creates a lot of extra code for Mips 16.
I had originally written a pattern for setge when the right operand is a
constant.
def: Mips16Pat
<(setge CPU16Regs:$lhs, immZExt16:$rhs),
(XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
(LiRxImmX16 1))>;
I was able to work around this boundary case by doing the reverse
transformation at the boundary.
i..e.
z = (x > (k-1)) => z = (x >= k)
def: Mips16Pat
<(setgt CPU16Regs:$lhs, -32769),
(XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
(LiRxImmX16 1))>;
2012 Aug 30
1
[LLVMdev] PHI
...machine block placement.
# Machine code for function main: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP-8]
fi#1: size=4, align=4, at location [SP-12]
fi#2: size=4, align=4, at location [SP-4]
Function Live Outs: %V0
BB#0: derived from LLVM BB %entry
%V0<def> = LiRxImmX16 <es:_gp_disp>[TF=5]
SaveRaF16 32
%V1<def> = AddiuRxPcImmX16 <es:_gp_disp>[TF=6]
%V0<def> = SllX16 %V0<kill>, 16
%S0<def> = AdduRxRyRz16 %V1<kill>, %V0<kill>
%V0<def> = LiRxImmX16 0
SwRxRyOffMemX16 %V0, %SP, 24; mem:...