search for: link_bw

...c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -76,10 +76,10 @@ nouveau_dp_detect(struct nouveau_encoder *nv_encoder) nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n", - nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); + nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); NV_DEBUG(drm, "encoder: %dx%d\n", - nv_encoder->dcb->dpconf.link_nr, - nv_encoder->dcb->dpconf.link_bw); + nv_encoder->dcb->dpconf.link_nr, + nv_encoder->dcb->dpconf.li...

This was already done in dcb.c inside nvkm, but the other parser did not get the update. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Entirely untested. Why do we have two DCB parsers again? Also the other one sets link_bw to a totally different set of units for link_bw... drm/nouveau/nouveau_bios.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nouveau_bios.c b/drm/nouveau/nouveau_bios.c index dd6fba55..c4ef3a0a 100644 --- a/drm/nouveau/nouveau_bios.c +++ b/drm/nouveau/nouveau...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f92..e17971a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nou...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f920bf89..e17971a30221 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/n...

...bool hdmi, u8 max_ac_packet, u8 rekey, u8 scdc, bool hda); int nvif_outp_acquire_lvds(struct nvif_outp *, bool dual, bool bpc8); -int nvif_outp_acquire_dp(struct nvif_outp *, u8 dpcd[16], +int nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], int link_nr, int link_bw, bool hda, bool mst); void nvif_outp_release(struct nvif_outp *); int nvif_outp_infoframe(struct nvif_outp *, u8 type, struct nvif_outp_infoframe_v0 *, u32 size); diff --git a/drivers/gpu/drm/nouveau/nvif/outp.c b/drivers/gpu/drm/nouveau/nvif/outp.c index 7da39f1eae9f..c24bc5eae3ec 100644 --- a/d...

...rekey, u8 scdc, bool hda); > > int nvif_outp_acquire_lvds(struct nvif_outp *, bool dual, bool bpc8); > > -int nvif_outp_acquire_dp(struct nvif_outp *, u8 dpcd[16], > > +int nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], > > int link_nr, int link_bw, bool hda, bool mst); > > void nvif_outp_release(struct nvif_outp *); > > int nvif_outp_infoframe(struct nvif_outp *, u8 type, struct nvif_outp_infoframe_v0 *, u32 size); > > diff --git a/drivers/gpu/drm/nouveau/nvif/outp.c b/drivers/gpu/drm/nouveau/nvif/outp.c > > index 7...

...t;link training!!\n"); + NV_DEBUG_KMS(dev, "link training!!\n"); train: cr_done = eq_done = false; /* set link configuration */ - NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n", + NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n", nv_encoder->dp.link_bw, nv_encoder->dp.link_nr); ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw); @@ -297,7 +297,7 @@ train: return false; /* clock recovery */ - NV_DEBUG(dev, "\tbegin cr\n"); + NV_DEBUG_KMS(dev, "\tbegin cr\n"); ret = nouveau_dp_link_train_set(encoder...

...int min_clock = 25000; + unsigned int max_clock, ds_clock, clock; + const u8 bpp = 18; /* 6 bpc */ enum drm_mode_status ret; if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace) return MODE_NO_INTERLACE; max_clock = outp->dp.link_nr * outp->dp.link_bw; - ds_clock = drm_dp_downstream_max_dotclock(outp->dp.dpcd, - outp->dp.downstream_ports); - if (ds_clock) - max_clock = min(max_clock, ds_clock); - - clock = mode->clock * (connector->display_info.bpc * 3) / 10; - ret = nouveau_conn_mode_clock_valid(mode, min_clock, max_clock, -...

...clock = mode->clock; if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace) return MODE_NO_INTERLACE; + if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) + clock *= 2; + max_clock = outp->dp.link_nr * outp->dp.link_bw; ds_clock = drm_dp_downstream_max_dotclock(outp->dp.dpcd, outp->dp.downstream_ports); @@ -245,9 +247,13 @@ nv50_dp_mode_valid(struct drm_connector *connector, max_clock = min(max_clock, ds_clock); clock = mode->clock * (connector->display_info.bpc * 3) / 10; - ret = no...

To start off: this patch series is less work to review then it looks - most (but not all) of the nouveau related work has already been reviewed elsewhere. Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f920bf89..e17971a30221 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/n...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f920bf89..e17971a30221 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/n...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f92..e17971a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nou...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index a72c412..49b5c10 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nou...

...n ret; + if (dpcd[DP_DPCD_REV] > 0x10) { + ret = nvkm_rdaux(aux, DP_DOWNSTREAM_PORT_0, + port_cap, DP_MAX_DOWNSTREAM_PORTS); + if (ret) + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); + } + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); + nv_encoder->dp.link_bw = 27000 * dpcd[1]; nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f92..e17971a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nou...

Just a backport of the two patches for v5.9 that you'll want to apply. The first one was Cc'd to stable, but I forgot to Cc the second one as well. Lyude Paul (2): drm/nouveau/kms/nv50-: Get rid of bogus nouveau_conn_mode_valid() drm/nouveau/kms/nv50-: Fix clock checking algorithm in nv50_dp_mode_valid() drivers/gpu/drm/nouveau/nouveau_connector.c | 36 ++++++---------------

...port_cap, DP_MAX_DOWNSTREAM_PORTS); > + if (ret) > + memset(port_cap, 0, DP_MAX_DOWNSTREAM_PORTS); > + } > + nv_encoder->dp.subconnector = drm_dp_subconnector_type(dpcd, port_cap); > + > nv_encoder->dp.link_bw = 27000 * dpcd[1]; > nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; > > diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h > index 3517f920bf89..e17971a30221 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_enco...

...b/nvkm/engine/disp/dport.c @@ -273,12 +273,15 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func, .outp = outp, .head = head, }, *dp = &_dp; - const u32 bw_list[] = { 270000, 162000, 0 }; + const u32 bw_list[] = { 540000, 270000, 162000, 0 }; const u32 *link_bw = bw_list; u8 hdr, cnt, len; u32 data; int ret; + if (nv_device(disp)->card_type < NV_D0) + link_bw++; + /* find the bios displayport data relevant to this output */ data = nvbios_dpout_match(bios, outp->hasht, outp->hashm, &dp->version, &hdr, &cnt, &a...

Hi all, I've frustrated myself the last few days yelling at our link training code. Comparing the i915 code to radeon and nouveau I've noticed the lack of a nice set of dp helper functions. So I've started to extract a few. There's lots more that we can do I think (link configuration selection, the i2c over aux retry stuff which diverges already between i915 and radeon, maybe

...return get_slave_funcs(encoder)->mode_valid(encoder, mode); case DCB_OUTPUT_DP: + if (mode->flags & DRM_MODE_FLAG_INTERLACE && + !nv_encoder->dp.caps.interlace) + return MODE_NO_INTERLACE; + max_clock = nv_encoder->dp.link_nr; max_clock *= nv_encoder->dp.link_bw; clock = clock * (connector->display_info.bpc * 3) / 10; diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 3517f920bf89..2a8a7aec48c4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h @...