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I'm relatively new to LLVM so apologies in advance if this is a dumb question. I've been experimenting with re-targeting LLVM onto a 16-bit micro which has pre and post increment and decrement addressing modes. I've been using llvm-gcc to generate llvm bitcode and llvm 2.7 to go from here to my target assembly code. I've got the Combine pass to deal with

Hi all, This is about a project I've been prototyping on-and-off for a while that has finally reached a point where I can claim it to be "potentially viable". I'd like to gather some input from the community before moving too far ahead. # The problem There is a representation issue within SCEV that prevents it from fully using information from nsw/nuw flags present in the