search for: lhszero

...ld be zero without // using the bits from the RHS. Below, we use knowledge about the RHS to // simplify the LHS, here we're using information from the LHS to simplify // the RHS. if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { APInt LHSZero, LHSOne; TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, LHSZero, LHSOne, Depth+1); // If the LHS already has zeros where RHSC does, this and is dead. if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) return TLO.C...

...ng the bits from the RHS. Below, we use knowledge about the > RHS to > // simplify the LHS, here we're using information from the LHS to > simplify > // the RHS. > if (ConstantSDNode *RHSC = > dyn_cast<ConstantSDNode>(Op.getOperand(1))) { > APInt LHSZero, LHSOne; > TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, > LHSZero, LHSOne, Depth+1); > // If the LHS already has zeros where RHSC does, this and is dead. > if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))...

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set