Displaying 2 results from an estimated 2 matches for "lhsshiftarg".
2007 Mar 30
1
[LLVMdev] Cleanups in ROTL/ROTR DAG combiner code
...==============================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp (.../trunk) (revision 2118)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp (.../branches/llvm-spu) (revision 2118)
@@ -1488,23 +1488,24 @@
}
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ SDOperand LHSShiftArg = LHSShift.getOperand(0);
+ SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+ SDOperand RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
- if (LHSShift.getOperand(1).getOpcode() == ISD:...
2013 Oct 03
2
[LLVMdev] Question about DAGCombiner::MatchRotate function
...ombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp (revision 191902)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp (working copy)
@@ -3415,12 +3415,16 @@
// (*ext (rotr x, (sub 32, y)))
SDValue LArgExtOp0 = LHSShiftArg.getOperand(0);
EVT LArgVT = LArgExtOp0.getValueType();
- if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
- SDValue V =
- DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
- LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAm...