Displaying 5 results from an estimated 5 matches for "lhsl".
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lhs
2008 Sep 08
0
[LLVMdev] adde/addc
...ollowing code to my target to do
the expansion:
ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
{
assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!");
// Extract components
SDOperand LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
N->getOperand(0),
DAG.getConstant(0, MVT::i32));
SDOperand LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
N->getOperand(0),
DAG.getConstant(1, MVT::i32));
SDOperand RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
N->getOperand(1),
DAG...
2008 Sep 08
6
[LLVMdev] adde/addc
My target doesn't support 64 bit arithmetic, so I'd like to supply
definitions for adde/addc. The problem is I can't seem to figure out the
magic. Here's an example of what I need to generate:
# two i64s in r5/r6 and r7/r8
# result in r1/r2, carry in r3
# adde
add r2, r6, r8
cmpltu r3, r2, r6 # compute carry
# addc
add r1, r5, r7
add r1, zero, r3
Is this
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...S.getValueType()), LHS,
- Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
- Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
- Tmp2 = SDValue();
- }
- LHS = LegalizeOp(Tmp1);
- RHS = Tmp2;
- return;
- }
-
- SDValue LHSLo, LHSHi, RHSLo, RHSHi;
- ExpandOp(LHS, LHSLo, LHSHi);
- ExpandOp(RHS, RHSLo, RHSHi);
- ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
-
- if (VT==MVT::ppcf128) {
- // FIXME: This generated code sucks. We want to generate
- // FCMPU crN, hi1, hi2
-...