Displaying 10 results from an estimated 10 matches for "lhshi".
2009 Dec 10
2
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
Eli,
I think I was able to get it working. Thanks for the help, does this look correct to you?
void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
DebugLoc dl = N->getDebugLoc();
EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(1), LoVT, HiVT);
Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, DAG.getValueType(LoVT));
Hi = DAG.getNode(N->getOpcode(), d...
2009 Dec 10
0
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
...gt;
> Eli,
> I think I was able to get it working. Thanks for the help, does this
> look correct to you?
>
> void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue
> &Lo,
> SDValue &Hi) {
> SDValue LHSLo, LHSHi;
> GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
> DebugLoc dl = N->getDebugLoc();
> EVT LoVT, HiVT;
> GetSplitDestVTs(N->getValueType(1), LoVT, HiVT);
>
> Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
> DAG.getValueType(LoVT));
>...
2009 Dec 10
0
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
Eli,
I don't see how this helps with the splitting of the Other node as it isn't the Dest that is the problem, but the second source value. Any place in the code that I can look at on how to split a VTSDNode?
Thanks,
Micah
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Thursday, December 10, 2009 1:25 PM
> To: Villmow, Micah
2009 Dec 10
0
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
...8 VTSDNode)>
So, how would I be able to split the Other node so that it will match the resulting data type?
My function looks like this:
void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
SDValue RHS = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHS);
Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHS);
}
Thanks,
Micah...
2009 Dec 10
2
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
On Thu, Dec 10, 2009 at 12:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Eli,
> I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS
2009 Dec 10
2
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
Thanks Eli,
I'll see if I can get something working and submit a patch.
Micah
-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com]
Sent: Wednesday, December 09, 2009 11:18 PM
To: Villmow, Micah
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
On Wed, Dec 9, 2009 at 8:40 PM, Villmow, Micah <Micah.Villmow at
2009 Dec 11
1
[LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported
...able to get it working. Thanks for the help, does this
> > look correct to you?
> >
> > void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N,
> SDValue
> > &Lo,
> > SDValue &Hi) {
> > SDValue LHSLo, LHSHi;
> > GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
> > DebugLoc dl = N->getDebugLoc();
> > EVT LoVT, HiVT;
> > GetSplitDestVTs(N->getValueType(1), LoVT, HiVT);
> >
> > Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
>...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...lueType()), LHS,
- Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
- Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
- Tmp2 = SDValue();
- }
- LHS = LegalizeOp(Tmp1);
- RHS = Tmp2;
- return;
- }
-
- SDValue LHSLo, LHSHi, RHSLo, RHSHi;
- ExpandOp(LHS, LHSLo, LHSHi);
- ExpandOp(RHS, RHSLo, RHSHi);
- ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
-
- if (VT==MVT::ppcf128) {
- // FIXME: This generated code sucks. We want to generate
- // FCMPU crN, hi1, hi2
- //...