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Hello, as discussed here in more detail: https://reviews.llvm.org/D81583 the introduction of the C++20 [[no_unique_address]] attribute exposes an ABI issue on platforms that require special handling for structs/classes that are "equivalent" to a single floating-point member (or in some cases, a "homogeneous" set of floating-point members). This is because we can now for the

...", LdStSync, > + [(int_ppc_sync)]>; > > //===----------------------------------------------------------------------===// > // PPC32 Arithmetic Instructions. > @@ -1357,5 +1361,13 @@ > def : Pat<(extloadf32 xaddr:$src), > (FMRSD (LFSX xaddr:$src))>; > > +// Memory barriers > +def : Pat<(membarrier (i32 imm:$ll), > + (i32 imm:$ls), > + (i32 imm:$sl), > + (i32 imm:$ss), > + (i32 imm:$device)), > + (SYNC)&gt...

...(ins), + "sync", LdStSync, + [(int_ppc_sync)]>; //===----------------------------------------------------------------------===// // PPC32 Arithmetic Instructions. @@ -1357,5 +1361,13 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; +// Memory barriers +def : Pat<(membarrier (i8 imm:$ll), + (i8 imm:$ls), + (i8 imm:$sl), + (i8 imm:$ss), + (i8 imm:$device)), + (SYNC)>; + include "PPCInstrAltivec.td"...

...+ "sync", LdStSync, + [(int_ppc_sync)]>; //===----------------------------------------------------------------------===// // PPC32 Arithmetic Instructions. @@ -1357,5 +1361,13 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; +// Memory barriers +def : Pat<(membarrier (i32 imm:$ll), + (i32 imm:$ls), + (i32 imm:$sl), + (i32 imm:$ss), + (i32 imm:$device)), + (SYNC)>; + include "PPCInstrAltivec.td&q...

...;> >> // >> = >> = >> = >> ----------------------------------------------------------------------= >> ==// >> // PPC32 Arithmetic Instructions. >> @@ -1357,5 +1361,13 @@ >> def : Pat<(extloadf32 xaddr:$src), >> (FMRSD (LFSX xaddr:$src))>; >> >> +// Memory barriers >> +def : Pat<(membarrier (i32 imm:$ll), >> + (i32 imm:$ls), >> + (i32 imm:$sl), >> + (i32 imm:$ss), >> + (i32 imm:$device)),...

On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > Hi all, > > I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled > my patch (attached) on the implementation in X86, but when I try and > compile my test file (also attached) with llc I get the error "Cannot > yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, > 0x10fa4be0,

This looks OK to check in, do you have write access? On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: > Dale Johannesen wrote: >> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: >>> I'm trying to implement llvm.memory.barrier on PowerPC. I've >>> modelled my patch (attached) on the implementation in X86, but >>> when I try and compile my test

...st", LdStSTWCX, + [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, + isDOT; //===----------------------------------------------------------------------===// // PPC32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.c...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...st", LdStSTWCX, + [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, + isDOT; //===----------------------------------------------------------------------===// // PPC32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.c...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...st", LdStSTWCX, + [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, + isDOT; //===----------------------------------------------------------------------===// // PPC32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.c...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...st", LdStSTWCX, + [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, + isDOT; //===----------------------------------------------------------------------===// // PPC32 Load Instructions. @@ -1327,9 +1355,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.c...