Displaying 2 results from an estimated 2 matches for "lfltbgg9ru0".
2016 Jan 07
3
BPF backend with vector operations - some strange error
Hello.
I've tried to add some simple arithmetic vector operations to the BPF backend
available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass
(taken from the Mips backend):
def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128,
(sequence "W%u", 0, 31)>;
in order to support vector for example, ADD
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
...ow). So far I'm not able to generate selection
code with TableGen for the ADD_r* instructions, etc:
def i64immSExt32 : PatLeaf<(imm),
[{return isInt<32>(N->getSExtValue()); }]>;
As in the case of https://groups.google.com/forum/#!topic/llvm-dev/LfltBGG9ru0 : "It
seems that defining a new register class changes how the tblgen infers the types in the
DAG patterns. So what is the right way to add a register class for a different type?"
Please help.
Thank you,
Alex
On 1/9/2016 9:29 PM, RCU wrote:
> Hello.
> (WRON...