search for: levenstein

Hi again, 2009/1/13 Evan Cheng <evan.cheng at apple.com>: > > > On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com> > wrote: > >> 2009/1/13 Evan Cheng <echeng at apple.com>: >>> >>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >>> >>>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>>> Predecessors acc...

On Thu, Mar 22, 2018 at 5:13 PM, Roman Levenstein via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On Thu, Mar 22, 2018 at 4:51 PM, Adrian Prantl <aprantl at apple.com> wrote: >> >> >>> On Mar 22, 2018, at 4:47 PM, Roman Levenstein <romixlev at gmail.com> wrote: >>> >>> Adrian, >>...

On Thu, Mar 22, 2018 at 4:51 PM, Adrian Prantl <aprantl at apple.com> wrote: > > >> On Mar 22, 2018, at 4:47 PM, Roman Levenstein <romixlev at gmail.com> wrote: >> >> Adrian, >> >> Thanks for a quick reply! >> >> On Thu, Mar 22, 2018 at 4:22 PM, Adrian Prantl <aprantl at apple.com> wrote: >>> >>> >>>> On Mar 22, 2018, at 4:08 PM, Roman Levenstein &l...

2009/1/13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0] >&gt...

On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com > wrote: > 2009/1/13 Evan Cheng <echeng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0)...

--- David Greene <greened at obbligato.org> wrote: > Roman Levenstein wrote: > > The allocator does not handle register aliases and register classes > > correctly, which makes it rather unusable for most architectures. > One > > idea that can be used for improving handling of irregular > architectures > > is described in the "A Gene...

...be interesting to hear what others think about - custom allocators, - reasons for current inefficiency of many STL containers on Evan's/Chris configs and - possibility of using 3rd party libs like Boost (or their parts) in LLVM Thanks, - Roman ----- Forwarded Mail ---- > From: Roman Levenstein <romix.llvm at googlemail.com> > To: CVS Commit Messages for LLVM repository <llvm-commits at cs.uiuc.edu> > Send: Friday, 16. May 2008, 19:20:29 > Subject: Re: [llvm-commits] Speeding up RegAllocLinearScan on big test-cases > > Hi, > > 2008/5/7 Evan Cheng : >...

...some thing else of the women decided to delivery some where else our health units. We managed to get the names from some other places but now we have to match our 4000 original names with over 20000 other names. To make thing more bitter some names have badly written. So I need some algorithm like Levenstein or sondex or phonix or something better already on R. Can you help me? Orvalho [[alternative HTML version deleted]]

Hi Evan, Thanks for your feedback! 2009/1/7 Evan Cheng <evan.cheng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from...

Hi Chris, Thanks for your response. > On Sat, 14 Oct 2006, Roman Levenstein wrote: > > Is it possible to dynamically define implicit defs for some > > instructions? > > Yes! This is what explicit operands are :). Specifically, if you > want to > vary on a per-opcode basis what registers are used/def'd by the > instruction, you can just a...

...ted LR restore. The register scavenger doesn't like this. The issue is while BL does modifies LR, it doesn't actually defines LR so later instructions can use it. I'll think about how to fix this. It's not obvious to me at this point. Evan On Jan 7, 2009, at 2:24 PM, Roman Levenstein wrote: > Hi Evan, > > Thanks for your feedback! > > 2009/1/7 Evan Cheng <evan.cheng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >> >> As you can see, PrologEpilogInserter has inserted at the beginning >> of th...

...__________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -- Statistics are like a bikini. What they reveal is suggestive, but what they conceal is vital (Aaron Levenstein) Kenneth Hoste ELIS - Ghent University kenneth.hoste at elis.ugent.be http://www.elis.ugent.be/~kehoste

> On Mar 22, 2018, at 4:47 PM, Roman Levenstein <romixlev at gmail.com> wrote: > > Adrian, > > Thanks for a quick reply! > > On Thu, Mar 22, 2018 at 4:22 PM, Adrian Prantl <aprantl at apple.com> wrote: >> >> >>> On Mar 22, 2018, at 4:08 PM, Roman Levenstein <romixlev at gmail.com> wro...

...cavenger doesn't like this. > > The issue is while BL does modifies LR, it doesn't actually defines LR > so later instructions can use it. I'll think about how to fix this. > It's not obvious to me at this point. > > Evan > > On Jan 7, 2009, at 2:24 PM, Roman Levenstein wrote: > >> Hi Evan, >> >> Thanks for your feedback! >> >> 2009/1/7 Evan Cheng <evan.cheng at apple.com>: >>> >>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >>> >>> >>> As you can see, PrologEpilogInserter...

Adrian, Thanks for a quick reply! On Thu, Mar 22, 2018 at 4:22 PM, Adrian Prantl <aprantl at apple.com> wrote: > > >> On Mar 22, 2018, at 4:08 PM, Roman Levenstein <romixlev at gmail.com> wrote: >> >> Hi, >> >> I'm trying to achieve the following: >> >> - I have a global variable BaseAddress that holds the base address of >> a contiguous dynamically allocated memory block. >> >> - I have a number...

On Thu, 21 Dec 2006, Roman Levenstein wrote: > following: > 1) some of the fixed registers intervals are merged with some virtual > registers intervals > 2) later there is a need to spill one of the allocated registers, but > since all joined intervals are FIXED intervals now due to (1), they > cannot be spilled. Ther...

Hi, In the LiveIntervalAnalysis::runOnMachineFunction, there is a code to compute the MBB2IdxMap, by remembering for each MBB its start and end instruction numbers: unsigned MIIndex = 0; for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); MBB != E; ++MBB) { unsigned StartIdx = MIIndex; for (MachineBasicBlock::iterator I = MBB->begin(), E =

Roman Levenstein wrote: > Hi Richard, > > Thanks for working on this! Your patched solved my initial problem, > but introduced another one. Please find attached another BC file that > fails on xcore with the linear scan regalloc. > > This is the error message I get > eliminateFrameIndex Fram...

...dience","research", "school"); string2 <- c("audience","push","drama","button","depending"); The words in string may occur in different order though. What function would you recommend to use to estimate similarity (e.g., levenstein, distance)? Appreciate for any advices. -Alex [[alternative HTML version deleted]]

On Wed, 4 Oct 2006, Roman Levenstein wrote: >> You can add the line >> setOperationAction(ISD::SELECT, MVT::i32, Expand); >> to the constructor of you TargetLowering class. See the current >> backend for an example. > > I actually tried it first. But then if, I remember correctly, SELECT > nodes were e...