search for: leros

Displaying 7 results from an estimated 7 matches for "leros".

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2016 Aug 01
3
testing a back-end pre-emit pass
Hi, Does anyone have any direction for me on testing a back-end pre-emit pass independently of other passes? The pass I'm looking at is a MachineFunctionPass, so the code is already using target-specific instructions. What I'm really looking to do is to see that the pass is correctly converting certain target-specific instructions sequences into other sequences, but I'm unsure how I
2016 Oct 19
4
[Sparc] vararg double issue on 32 bit Sparc processors
Hi, I've discovered a problem on Sparc processors (specifically, LEON, but I suspect but can't verify that it also happens on all Sparc processors). The problem is, or appears to be with using double values in Sparc (32 bit). Specifically, double values are not being loaded into registers correctly within a function using va_args. Only half the value is loaded (i.e. 32, rather than 64
2016 Jan 28
2
Vectors in Sparc
The following code is causing me problems in the Sparc back-end and I believe it's related to a lot of issues that I have, so I'd love to work out what I need to do to resolve this. I'm currently not making much headway into it. I'm going to try to simplify this to the core problem I can see and hope I haven't missed anything relevant. The original code I have is as follows:
2016 Apr 15
3
[Sparc] Load address with SETHI
Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a
2016 Nov 16
6
[SPARC]: leon2 and leon3: not respecting delayed-write to Y-register
Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.
1999 Aug 02
1
NULL filled corrupt files
Hello! I've seen, some people experienced this problem earlyer, but I have not found any solution in the mailing lists... So the problem is, copying files from an NT Workstation (SP5 ) on a Samba server running under Linux (2.0.10) in some (rare) cases results in files exactly of the right size but filled with NULL bytes. I'm using samba 2.0.5a and likely since version 2.0.0 this
2015 Sep 18
5
multiply-accumulate instruction
I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made