search for: lero

...er sequences, but I'm unsure how I can get an input in the correct format to construct a good unit test. Can I generate an ".ll" file using target specific instructions and then pass it through to a back-end MachineFunctionPass to test specifically just that one pass? Chris Dewhurst, Lero, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160801/e78b3cc6/attachment.html>

...n provide more details on specifics, but rather than head off into excessive details immediately, I'd appreciate if anyone can help me identify what direction I really should be taking to fix this problem. I'm not convinced I've been going about it the right way so far. Chris Dewhurst, Lero, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161019/6e832839/attachment.html>

...9;d prefer to do the first of these and get the vectors represented as registers. This seems more efficient. Any help pointing me in the right direction will be greatly appreciated. I don't suppose there's anything as simple a a clang command-line flag that will do this??? Chris Dewhurst, LERO, The Irish Software Research Centre, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160128/fea79406/attachment.html>

...c. I imagine this is similar if I try to make a CALLRi or CALLrr call, but looking through the code there isn't yielding any obvious solution to me. Would anyone be able to point me at a relevant piece of code that can do this, or is already doing it for Sparc? Best Regards, Chris Dewhurst / Lero, University of Limerick, Ireland. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160415/43d52775/attachment.html>

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

Hello! I've seen, some people experienced this problem earlyer, but I have not found any solution in the mailing lists... So the problem is, copying files from an NT Workstation (SP5 ) on a Samba server running under Linux (2.0.10) in some (rare) cases results in files exactly of the right size but filled with NULL bytes. I'm using samba 2.0.5a and likely since version 2.0.0 this

I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made