Displaying 20 results from an estimated 111 matches for "lendacky".
2020 Apr 14
3
[PATCH 40/70] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
On 4/14/20 2:03 PM, Mike Stunes wrote:
> On Mar 19, 2020, at 2:13 AM, Joerg Roedel <joro at 8bytes.org> wrote:
>>
>> From: Tom Lendacky <thomas.lendacky at amd.com>
>>
>> The runtime handler needs a GHCB per CPU. Set them up and map them
>> unencrypted.
>>
>> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
>> Signed-off-by: Joerg Roedel <jroedel at suse.de>
>> ---...
2020 Apr 14
3
[PATCH 40/70] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
On 4/14/20 2:03 PM, Mike Stunes wrote:
> On Mar 19, 2020, at 2:13 AM, Joerg Roedel <joro at 8bytes.org> wrote:
>>
>> From: Tom Lendacky <thomas.lendacky at amd.com>
>>
>> The runtime handler needs a GHCB per CPU. Set them up and map them
>> unencrypted.
>>
>> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
>> Signed-off-by: Joerg Roedel <jroedel at suse.de>
>> ---...
2020 Feb 11
0
[PATCH 03/62] x86/cpufeatures: Add SEV-ES CPU feature
From: Tom Lendacky <thomas.lendacky at amd.com>
Add CPU feature detection for Secure Encrypted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
S...
2020 Feb 11
0
[PATCH 01/62] KVM: SVM: Add GHCB definitions
From: Tom Lendacky <thomas.lendacky at amd.com>
Extend the vmcb_safe_area with SEV-ES fields and add a new
'struct ghcb' which will be used for guest-hypervisor communication.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arc...
2020 Feb 11
0
[PATCH 46/62] x86/sev-es: Handle INVD Events
From: Tom Lendacky <thomas.lendacky at amd.com>
Implement a handler for #VC exceptions caused by INVD instructions.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
[ jroedel at suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel <jroedel at suse.de>
Signed-off-by...
2020 Feb 11
0
[PATCH 50/62] x86/sev-es: Handle VMMCALL Events
From: Tom Lendacky <thomas.lendacky at amd.com>
Implement a handler for #VC exceptions caused by VMMCALL instructions.
This patch is only a starting point, VMMCALL emulation under SEV-ES
needs further hypervisor-specific changes to provide additional state.
Signed-off-by: Tom Lendacky <thomas.lendacky at a...
2020 Feb 11
1
[PATCH 19/62] x86/sev-es: Add support for handling IOIO exceptions
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Tom Lendacky <thomas.lendacky at amd.com>
>
> Add support for decoding and handling #VC exceptions for IOIO events.
>
> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
> [ jroedel at suse.de: Adapted code to #VC handling framework ]
> Co-developed-by: Joerg Roedel <jroe...
2020 Feb 12
1
[PATCH 46/62] x86/sev-es: Handle INVD Events
> On Feb 11, 2020, at 5:53 AM, Joerg Roedel <joro at 8bytes.org> wrote:
>
> ?From: Tom Lendacky <thomas.lendacky at amd.com>
>
> Implement a handler for #VC exceptions caused by INVD instructions.
Uh, what? Surely the #VC code can have a catch-all OOPS path for things like this. Linux should never ever do INVD.
2020 Feb 11
0
[PATCH 41/62] x86/sev-es: Handle MSR events
From: Tom Lendacky <thomas.lendacky at amd.com>
Implement a handler for #VC exceptions caused by RDMSR/WRMSR
instructions.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
[ jroedel at suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel <jroedel at suse.de>
Signed...
2020 Apr 28
0
[PATCH v3 01/75] KVM: SVM: Add GHCB definitions
From: Tom Lendacky <thomas.lendacky at amd.com>
Extend the vmcb_safe_area with SEV-ES fields and add a new
'struct ghcb' which will be used for guest-hypervisor communication.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arc...
2020 Apr 28
0
[PATCH v3 59/75] x86/sev-es: Handle MONITOR/MONITORX Events
From: Tom Lendacky <thomas.lendacky at amd.com>
Implement a handler for #VC exceptions caused by MONITOR and MONITORX
instructions.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
[ jroedel at suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel <jroedel at suse.de&g...
2020 Apr 28
0
[PATCH v3 53/75] x86/sev-es: Handle MSR events
From: Tom Lendacky <thomas.lendacky at amd.com>
Implement a handler for #VC exceptions caused by RDMSR/WRMSR
instructions.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
[ jroedel at suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel <jroedel at suse.de>
Signed...
2020 Aug 24
0
[PATCH v6 02/76] KVM: SVM: Add GHCB definitions
From: Tom Lendacky <thomas.lendacky at amd.com>
Extend the vmcb_safe_area with SEV-ES fields and add a new
'struct ghcb' which will be used for guest-hypervisor communication.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arc...
2020 Aug 28
0
[PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler
On Thu, Aug 27, 2020 at 06:48:10PM -0400, Arvind Sankar wrote:
> On Mon, Aug 24, 2020 at 10:54:22AM +0200, Joerg Roedel wrote:
> > From: Tom Lendacky <thomas.lendacky at amd.com>
> >
> > Handle #VC exceptions caused by CPUID instructions. These happen in
> > early boot code when the KASLR code checks for RDTSC.
> >
> > Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
> > [ jroedel at suse...
2020 Apr 28
0
[PATCH v3 04/75] x86/cpufeatures: Add SEV-ES CPU feature
From: Tom Lendacky <thomas.lendacky at amd.com>
Add CPU feature detection for Secure Encrypted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
S...
2020 May 20
1
[PATCH v3 51/75] x86/sev-es: Handle MMIO events
On Tue, Apr 28, 2020 at 05:17:01PM +0200, Joerg Roedel wrote:
> From: Tom Lendacky <thomas.lendacky at amd.com>
>
> Add handler for VC exceptions caused by MMIO intercepts. These
> intercepts come along as nested page faults on pages with reserved
> bits set.
>
> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
> [ jroedel at suse.de: Ad...
2020 Feb 11
0
[PATCH 35/62] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
From: Tom Lendacky <thomas.lendacky at amd.com>
The runtime handler needs a GHCB per CPU. Set them up and map them
unencrypted.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
arch/x86/kernel...
2020 Feb 11
1
[PATCH 35/62] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Tom Lendacky <thomas.lendacky at amd.com>
>
> The runtime handler needs a GHCB per CPU. Set them up and map them
> unencrypted.
>
> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
> Signed-off-by: Joerg Roedel <jroedel at suse.de>
> ---
> arch/x86/include/asm/...
2020 Sep 07
0
[PATCH v7 41/72] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
From: Tom Lendacky <thomas.lendacky at amd.com>
The runtime handler needs a GHCB per CPU. Set them up and map them
unencrypted.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
arch/x86/kernel...
2020 Apr 28
0
[PATCH v3 43/75] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
From: Tom Lendacky <thomas.lendacky at amd.com>
The runtime handler needs a GHCB per CPU. Set them up and map them
unencrypted.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
arch/x86/kernel...