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...all analysis are done on SCEVs. The SCEV generator can transform them even without the need for explicit canonical induction variables. Best, Tobias On Wed, Aug 9, 2017, at 14:23, Anastasiya Ruzhanskaya via llvm-dev wrote: > The files of this strange pass are described here > http://reviews.legup.org/rLEGUP54ca7c2bb15d84116baf47bce67256d3803720d9 > . > I wonderwhy the most uptodate -indvars pass can't do the same. > > 2017-08-09 14:18 GMT+02:00 Anastasiya Ruzhanskaya < > anastasiya.ruzhanskaya at frtk.ru>: > > > Hello, > > I have this piece of code...

...(i8*, ...) @printf(i8* nonnull getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i32 %l.01) %4 = add nuw nsw i32 %l.01, 4 %5 = icmp slt i32 %4, 1000 br i1 %5, label %2, label %1 } I have this assembler. I know there is indvars2 pass ( it is under llvm license but used only in LegUp project - as I understood, surfing the Internet), which is good in changing induction variables. How can I achieve that this cycle will have a canonical indvar? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/...

...timate Buchi Automizer (https://ultimate.informatik.uni-freiburg.de/downloads/BuchiAutomizer/). This is a tool that tries to prove termination or infinite execution for some programs. * We can check how many programs can be compiled by different high-level synthesis tools into FPGAs. We have tried LegUp and Vivado, for instance. * Our webpage contains a search box, so that you can get the closest programs to a given input program. Currently, we measure program distance as the Euclidian distance on Namolaru feature vectors. We do not currently provide inputs for those programs. It's possible...

...ik.uni-freiburg.de/downloads/BuchiAutomizer/). > > This is a tool that tries to prove termination or infinite execution > > for some programs. > > > > * We can check how many programs can be compiled by different > > high-level synthesis tools into FPGAs. We have tried LegUp and Vivado, > > for instance. > > > > * Our webpage contains a search box, so that you can get the closest > > programs to a given input program. Currently, we measure program > > distance as the Euclidian distance on Namolaru feature vectors. > > > > We do...

...used these benchmarks in two studies: 1) http://cuda.dcc.ufmg.br/angha/chordAnalysis 2) http://cuda.dcc.ufmg.br/angha/staticProperties A few other applications that I know about (outside our research group), include: * Comparing the size of code produced by three HLS tools: Intel HLS, Vivado and LegUp. * Testing the Ultimate Buchi Automizer, to see which kind of C constructs it handles * Comparing compilation time of gcc vs clang A few other studies that I would like to carry out: * Checking the runtime of different C parsers that we have. * Trying to infer, empirically, the complexity of comp...

...I'm using because it doesn't seem to be implemented in gem5 otherwise, and would simply produce a warning). Then my guess is that I should use something like: def CACHEADD : I<0x16, FORMAT, (outs), (ins), ASM, [(int_cache_add)]>, PD; where FORMAT comes from http://legup.eecg.utoronto.ca/doxygen/namespacellvm_1_1X86II.html and ASM = ??? and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag indicates, but I assume it's not needed). I'm not sure what that PD is or if it should stay. Looking for input on this! Clearly it's not correct a...

folks hi, something i just wanted to double-check. is it possible to use, with LLVM, entirely free software tools to build and upload to a xilinx microblaze FPGA target? i take some c code, put it through llvm-fpga, aaand... then what? is there any documentation about this stuff, anywhere? tia, l.

...; doesn't seem to be implemented in gem5 otherwise, and would simply produce > a warning). Then my guess is that I should use something like: > def CACHEADD : I<0x16, FORMAT, (outs), (ins), > ASM, [(int_cache_add)]>, PD; > > where FORMAT comes from http://legup.eecg.utoronto.ca/doxygen/ > namespacellvm_1_1X86II.html > and ASM = ??? > and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag > indicates, but I assume it's not needed). > I'm not sure what that PD is or if it should stay. > > Looking for input on t...

...o be implemented in gem5 otherwise, and would simply produce >> a warning). Then my guess is that I should use something like: >> def CACHEADD : I<0x16, FORMAT, (outs), (ins), >> ASM, [(int_cache_add)]>, PD; >> >> where FORMAT comes from http://legup.eecg.utoront >> o.ca/doxygen/namespacellvm_1_1X86II.html >> and ASM = ??? >> and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag >> indicates, but I assume it's not needed). >> I'm not sure what that PD is or if it should stay. >> &gt...

I forgot to cc the list On Mon, Oct 11, 2010 at 6:19 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > Well this is my 20,000 foot viewpoint of the project you have > described. Also, I would appreciate if someone more knowledgeable > revised my statements. > > First, I would make a mock machine with large register banks for each > kind of operation and size combination. The

Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to