search for: legaltypes

...s and illegal operations. After type legalization but before operation legalization it is allowed to create nodes with illegal operations, but all types must be legal. After operation legalization it is only allowed to create fully legal nodes. Inside DAGCombine this is specified by two flags: LegalTypes being true means that all nodes must have legal types. LegalOperations being true means that all nodes must have legal operations (as well as types: LegalTypes will also be true). So if LegalTypes is true and nonetheless a constant with an illegal type is being created then that is a DAG combine...

Right. DAGCombine will insert *illegal* nodes before legalize. Evan On Jan 19, 2009, at 8:17 PM, Eli Friedman wrote: > On Mon, Jan 19, 2009 at 6:36 PM, Scott Michel <scottm at aero.org> wrote: >> I just ran across something interesting: DAGCombine inserts a 64-bit >> constant as the result of converting a (bitconvert (fabs val)) to a >> (and (bitconvert val),

...ter type legalization but before operation legalization > it is allowed to create nodes with illegal operations, but all types > must be legal. After operation legalization it is only allowed to > create fully legal nodes. > > Inside DAGCombine this is specified by two flags: > LegalTypes being true means that all nodes must have legal types. > LegalOperations being true means that all nodes must have legal > operations (as well as types: LegalTypes will also be true). > > So if LegalTypes is true and nonetheless a constant with an > illegal type is being created th...

On Tue, Jan 20, 2009 at 12:24 AM, Duncan Sands <baldrick at free.fr> wrote: > So if LegalTypes is true and nonetheless a constant with an > illegal type is being created then that is a DAG combiner bug. The issue here isn't that i64 is illegal, it's that constants of type i64 are illegal. I'm tempted to say that having legal constants should be a requirement for marking an i...

...eration > legalization > > it is allowed to create nodes with illegal operations, but all types > > must be legal. After operation legalization it is only allowed to > > create fully legal nodes. > > > > Inside DAGCombine this is specified by two flags: > > LegalTypes being true means that all nodes must have legal types. > > LegalOperations being true means that all nodes must have legal > > operations (as well as types: LegalTypes will also be true). > > > > So if LegalTypes is true and nonetheless a constant with an > > illegal...

...Op0.getOpcode() == ISD::XOR) { >> TheXor = Op0.getNode(); >> Equal = true; >> } >> >> SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; >> >> EVT SetCCVT = NodeToReplace.getValueType(); >> if (LegalTypes) >> SetCCVT = TLI.getSetCCResultType(SetCCVT); >> SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), >> SetCCVT, >> Op0, Op1, >> Equal ? ISD:...

...avoid a constant pool spill"). In many respects, DAGCombine and operation Legalize are co-routines, not separate passes. -scooter On Jan 20, 2009, at 1:23 AM, Eli Friedman wrote: > On Tue, Jan 20, 2009 at 12:24 AM, Duncan Sands <baldrick at free.fr> > wrote: >> So if LegalTypes is true and nonetheless a constant with an >> illegal type is being created then that is a DAG combiner bug. > > The issue here isn't that i64 is illegal, it's that constants of type > i64 are illegal. I'm tempted to say that having legal constants > should be a requi...

...etAPIntValue() == 1 && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR) { TheXor = Op0.getNode(); Equal = true; } SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; EVT SetCCVT = NodeToReplace.getValueType(); if (LegalTypes) SetCCVT = TLI.getSetCCResultType(SetCCVT); SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), SetCCVT, Op0, Op1, Equal ? ISD::SETEQ : ISD::SETNE); // Replace the u...

...OneUse() && > Op0.getOpcode() == ISD::XOR) { > TheXor = Op0.getNode(); > Equal = true; > } > > SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; > > EVT SetCCVT = NodeToReplace.getValueType(); > if (LegalTypes) > SetCCVT = TLI.getSetCCResultType(SetCCVT); > SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), > SetCCVT, > Op0, Op1, > Equal ? ISD::SETEQ : ISD::SETNE); &gt...

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >