search for: legalizer

Displaying 20 results from an estimated 10019 matches for "legalizer".

Did you mean: legalize
2009 Jan 20
2
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
Duncan: DAGCombine is inserting an IllegalOperation after target-specific instruction legalization has occurred. I'm inserting the fabs and the bitconvert during instruction legalization; DAGCombine is converting the fabs/bitconvert to an 'and' on its second (third?) pass. -scooter On Jan 20, 2009, at 12:24 AM, Duncan Sands wrote: > On Tuesday 20 January 2009 07:52:37
2009 Jan 20
5
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
Right. DAGCombine will insert *illegal* nodes before legalize. Evan On Jan 19, 2009, at 8:17 PM, Eli Friedman wrote: > On Mon, Jan 19, 2009 at 6:36 PM, Scott Michel <scottm at aero.org> wrote: >> I just ran across something interesting: DAGCombine inserts a 64-bit >> constant as the result of converting a (bitconvert (fabs val)) to a >> (and (bitconvert val),
2009 Jan 20
0
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
On Tuesday 20 January 2009 07:52:37 Evan Cheng wrote: > Right. DAGCombine will insert *illegal* nodes before legalize. There are two stages of legalization: legalization of types, followed by legalization of operations. Before type legalization DAGCombine is allowed to create nodes with illegal types and illegal operations. After type legalization but before operation legalization it is
2019 Jan 07
2
GlobalISel legalization artifact legalization
...h splitting/scalarization and keep running into similar sorts of issues which are making me question the intended function of the various legalization operations (particularly G_MERGE_VALUES/G_UNMERGE_VALUES, but also G_EXTRACT/G_INSERT and conversion instructions) and what the contract between the legalizer and selector actually is. For scalar values, things seem clearer, but I’m still confused. The AArch64 selector code seems content to allow strange sized values in the source of G_EXTRACT/G_SEXT etc, and then just set the register class as the type information isn’t really needed anymore. However,...
2020 Oct 07
2
GlobalISel round table follow-up: multi-stage legalization
Hi all, first of all thanks to Matt for hosting the round table yesterday and to everyone else for their time and the valuable discussions. As promised in the chat yesterday, here is the email regarding the legalizer / artifact combiner issue we talked about. I will send a separate email regarding the regbankselect discussion. In case someone on the list didn't attend the round table yesterday, here is quick summary: One problem that some of us are seeing in the legalizer is that sometimes instruction...
2020 Jan 28
2
Handling node through TargetLowering::LowerOperation vs TargetLowering::ReplaceNodeResults
...s of the node are illegal? Or actually such situation is impossible and for given node either LowerOperation or ReplaceNodeResults can be only called? Przemek wt., 28 sty 2020, 18:48 użytkownik Craig Topper <craig.topper at gmail.com> napisał: > ReplaceNodeResults is called by the type legalizer for custom legalizing > any of the results of a node that have an illegal type. > > LowerOperation is called by the type legalizer to custom legalize node > inputs that have an illegal type. I believe technically it calls > LowerOperationWrapper, but that forwards to LowerOperation b...
2009 Mar 05
2
[LLVMdev] visitBIT_CONVERT (previous Shouldn't DAGCombine insert legal nodes?)
Hello, In the combine 2 step (after legalization), in the DAGCombiner::visitBIT_CONVERT() method, the DAG combiner is replacing an FABS followed by a BIT_CONVERT, to a BIT_CONVERT followed by an AND 0x7FFFFFFFFFFFFFFF. Everything is 64 bit. On my target, FABS and BIT_CONVERT are legal in 64 bit, but AND in not legal in 64 bit (is declared custom). So the dag combiner is introducing illegal (not
2018 Sep 13
2
[GlobalISel][MIPS] Legality and instruction combining
Hello, I am developing GlobalISel for MIPS. I have a few questions and observations about defining legality of generic instruction and also possible combining of instructions and artifacts in pre/post legalizer combiner or elsewhere (e.g. in some sort of instruction-select patterns). I look at legality as "If generic instruction can be selected into machine instruction, it is legal". For example, let's look at G_ICMP and G_SELECT. In llvm IR type of result of icmp is always i1, and test ar...
2014 Sep 26
2
[LLVMdev] Use of custom operations after DAG legalization
I've been working on a backend for a 16-bit microcontroller and I've just updated my base from LLVM 3.4 to LLVM 3.5.0. This threw up a regression failure in my test suite, and having tracked down the cause, I'm now confused about the DAG legalization and optimization process which I thought I understood. I'd be really grateful for advice on whether I've misunderstood how
2009 May 22
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...LegalizeVectors then, since it handles more than just vectors? Perhaps something like LegalizeOpsNeedingNewTypes? I haven't looked into details, but I think the approach in the patch looks reasonable. Adding yet another pass is somewhat undesirable, though it's better than having two type legalizers, and better than having a complicated scheme to call back into LegalizeTypes. And we can always revisit this in the future. Dan
2018 Jun 29
2
[RFC][VECLIB] how should we legalize VECLIB calls?
Ashutosh, Thanks for the repy. Related earlier topic on this appears in the review of the SVML patch (@mmasten). Adding few names from there. https://reviews.llvm.org/D19544 There, I see Hal's review comment "let's start only with the directly-legal calls". Apparently, what we have right now in the trunk is "not legal enough". I'll work on the patch to stop
2018 Jun 29
2
[RFC][VECLIB] how should we legalize VECLIB calls?
Illustrative Example: clang -fveclib=SVML -O3 svml.c -mavx #include <math.h> void foo(double *a, int N){ int i; #pragma clang loop vectorize_width(8) for (i=0;i<N;i++){ a[i] = sin(i); } } Currently, this results in a call to <8 x double> __svml_sin8(<8 x double>) after the vectorizer. This is 8-element SVML sin() called with 8-element argument. On the surface,
2009 Feb 02
4
[LLVMdev] type legalizer promoting BUILD_VECTORs
LLVM's type legalizer is changing the types of BUILD_VECTORs in a way that seems wrong to me, but I'm not sure if this is a bug or if some targets may be relying on it. On a 32-bit target, the default action for legalizing i8 and i16 types is to promote them. If you then have a BUILD_VECTOR to construct a...
2018 Sep 21
2
[GlobalISel] Legalize generic instructions that also depend on type of scalar, not only scalar size
...html for G_LOAD/G_STORE. Legality of an instruction should not depend on surrounding instructions. Because of that, approach from regbankselect that iterates through uses of G_LOAD def register and checks if some of the uses was an generic floating point instruction should not be an option for legalizer. Since GlobalISel Legalizer cannot distinguish between them using only LLT, only other option that I can see at this moment is having "F" variant of the generic instruction (like this is the case with G_ADD and G_FADD). Is this change possible? Or are there some other approaches for...
2015 Mar 04
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
...ob is to canonicalize so that other > (perhaps target-specific) transformations only need to handle the > canonical representation. Usually, that means optimizing code: stuff > like e.g. (sub x, x) shouldn't be special-cased in each target (at > least not on ISD nodes ;)) > The legalizer (or rather, the various legalizers) later does its own > job, legalizing, after which all code must be "legal". The further > rounds of DAGCombining just maintain that invariant. > > So really, this is a legalization problem: for instance, is it not > possible for the Sel...
2018 Jul 02
2
[RFC][VECLIB] how should we legalize VECLIB calls?
Adding to Ashutosh's comments, We are also interested in making LLVM generate vector math library calls that are available with glibc (version > 2.22). reference: https://sourceware.org/glibc/wiki/libmvec Using the example case given in the reference, we found there are 2 vector versions for "sin" (4 X double) with same VF namely _ZGVcN4v_sin (avx) version and _ZGVdN4v_sin
2008 Oct 01
3
[LLVMdev] Type Legalizer Question.
On Wed, 2008-10-01 at 11:12 +0200, Duncan Sands wrote: > Hi, > > > I have another query related to type legalizer. > > Can a target ignore certain nodes during legalize? Probably a hook for > > target that can be called inside IgnoreNodeResults ()? > > while this could be done, I don't like the idea of doing an end-run > around the whole type legalization infrastructure. So you would...
2008 Oct 02
3
[LLVMdev] Type Legalizer Question.
...ve to custom >>> lower all other i16 operations. This will work, but it requires a lot >>> of target specific code. >> >> True. If we add the i16 reg class we will need to write a lot of >> target specific code. >> To avoid that our idea was not to tell the legalizer about the i16 >> regclass and let it expand everything but ignore the pointers. > > You can try just marking all i16 operations, other than load and > store, as "expand". Would that work? Won't work; LLVM expects at least some basic operations, like add, to be legal in...
2009 Jan 20
3
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
I just ran across something interesting: DAGCombine inserts a 64-bit constant as the result of converting a (bitconvert (fabs val)) to a (and (bitconvert val), i64const). The problem: i64 constants have to be legalized for the CellSPU platform. DAGCombine is doing the right thing but it's not doing the right thing for CellSPU and it's damed difficult to work around this
2015 Jan 25
4
[LLVMdev] RFB: Would like to flip the vector shuffle legality flag
I ran the benchmarking subset of test-suite on a btver2 machine and optimizing for btver2 (so enabling AVX codegen). I don't see anything outside of the noise with x86-experimental-vector-shuffle-legality=1. On Fri, Jan 23, 2015 at 5:19 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > On Fri, Jan 23, 2015 at 8:15 AM, Chandler Carruth