search for: leas

Hi, Here is an update on our proposal to improve the uses of LEA on Atom processors. 1. Disable current generation of LEAs Due to a 3 cycle stall between the ALU and the AGU any address generation done using math instruction will cause a stall on loads and stores which are within 3 cycles of the address generation. Consequently, the heuristics for using LEAs efficiently must know how many cycles pass between the addre...

...s a lea for the testcase in llvm.org/pr13320. On 28 September 2012 11:36, Nowicki, Tyler <tyler.nowicki at intel.com> wrote: > Hi, > > > > Here is an update on our proposal to improve the uses of LEA on Atom > processors. > > > > 1. Disable current generation of LEAs > > > > Due to a 3 cycle stall between the ALU and the AGU any address generation > done using math instruction will cause a stall on loads and stores which are > within 3 cycles of the address generation. Consequently, the heuristics for > using LEAs efficiently must know how...

This patch introduces an optimized assembler version of md5_process(), the inner loop of MD5 checksumming. It affects the performance of all MD5 operations in rsync - including block matching and whole-file checksums. Performance gain is 5-10% depending on the specific CPU. Originally created by Marc Bevand and placed in the public domain, later integrated into OpenSSL. This is the original

Hello everyone, In the file *lib/CodeGen/AsmPrinter/AsmPrinter.cpp*, I would like to obtain an MCInst corresponding to its MachineInstr. Can anyone tell me a way to do that? If that is not possible, then, I would like to know if a given MachineInstr is an *lea *instruction and I would like to know if the symbol involved with this lea instruction is a jump-table. For instance, given a

Hi, We are getting ready to implement several heuristics for correctly using LEAs to avoid stalls in the address generator on Atom. Our plan is to: 1. Disabling LEA generation on Atom in X86ISelDAGToDAG:: SelectLEAAddr() for all but a few pseudo-instructions 2. Identify loads and stores in a X86PassConfig::addPreEmitPass() pass and examine several preceding instru...

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I submitted the problem report to clang's bugzilla but no one seems to care so I have to send it to the mailing list. clang 3.7 svn (trunk 229055 as the time I was to report this problem) generates slower code than 3.5 (Apple LLVM version 6.0 (clang-600.0.56) (based on LLVM 3.5svn)) for the following code. It is a "8 queens puzzle" solver written as an educational example. As

> Anyway, thanks very much for the information. Hopefully that'll let me > track things down. Let me know if you need some more information or dumps. > Would you mind me taking a day or so to investigate what's going on > here properly? Introducing a volatile to work around a bug in Clang > itself just seems perverse to me. (And we shouldn't let a CodeGen bug >

The regressions in the performance of generated code, introduced by the llvm 3.6 release, don't seem to be limited to this 8 queens puzzle" solver test case. See... http://www.phoronix.com/scan.php?page=article&item=llvm-clang-3.5-3.6-rc1&num=1 where a bit hit in the performance of the Sparse Matrix Multiply test of the SciMark v2.0 benchmark was observed as well as...

I've got a question about instruction selection for a backend I'm writing. The target has two register classes, RC1 and RC2. The instruction set is far from orthogonal. The ADD instruction is two address with both register/immediate and register/memory forms. The register operand is in the RC1 class. The LEA instruction is three address with the destination register in the RC2 class.

...e from http://math.nist.gov/scimark2/scimark2_1c.zip compiled with the same... make CFLAGS="-O3 -march=native" I am able to reproduce the 22% performance regression in the run time of the Sparse matmult benchmark. For 10 runs of the scimark2 benechmark, I get 998.439+/-0.4828 with the release llvm clang 3.5.1 compiler and 1217.363+/-1.1004 for the current clang 3.6svn from 3.6 branch. Not good. Jack On Sat, Feb 14, 2015 at 11:19 AM, Jack Howarth <howarth.mailing.lists at gmail.com> wrote: > Do any of the build-bots routinely run the SciMark v2.0 benchma...

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Hi david, I find you signed off a patch about "x86: emulate lea with two register operands correctly" .In this patch,you described skype does a lea instruction and will crash when starting if it does not get the exception.I have used a tool named mentorKG.exe to make a LICENSE.TXT.but the software crashes when starting.I used your patch,and find it works well.I wonder how can you

...bly need a profitability target hook which knows about lea. We should also consider disabling it's dumb pseudo scheduling code when we enable MI scheduler. Sorry, I set this aside to look at closely and never got back to it. The lea->cmp problem is fixed by switching to the MI scheduler. Please run with -mllvm -misched-bench to confirm. Leaving the old ILP scheduler as the default continues to cause confusion. People have had plenty of time to evaluate the new scheduler. I’ll plan to switch the default for x86 on Monday. Now, that doesn’t mean that your analysis of the 2-address pass i...

Pretty sure you need to check EAX>=7 from cpuid leaf 0 before calling leaf 7 and you need to use the pass ECX=0 to leaf 7. See lib/Target/X86/X86Subtarget.cpp which uses a GetX86CpuIDAndInfoEx function to pass EAX and ECX to cpuid. I don't think it explains your compiler bug though. On Thu, Sep 12, 2013 at 2:12 PM, Adam Strzelecki <ono at java.pl> wrote: > > Anyway, thanks

...is free software: you are free to change and redistribute it. > There is NO WARRANTY, to the extent permitted by law. Type "show copying" > and "show warranty" for details. > This GDB was configured as "x86_64-linux-gnu". > For bug reporting instructions, please see: > <http://bugs.launchpad.net/gdb-linaro/>... > Reading symbols from > /home/zdevito/clang+llvm-3.4-x86_64-unknown-ubuntu12.04/bin/lli...(no > debugging symbols found)...done. > (gdb) b showdebug.c:6 > No symbol table is loaded. Use the "file" command. > M...

So here is quick patch solving the problem, now it should be PIC. -- Miroslav Lichvar lichvarm@phoenix.inf.upol.cz -------------- next part -------------- --- lpc_asm.nasm.orig Wed Jul 18 02:23:40 2001 +++ lpc_asm.nasm Sat Nov 17 21:09:46 2001 @@ -59,10 +59,10 @@ ; ALIGN 16 cident FLAC__lpc_compute_autocorrelation_asm_ia32 - ;[esp + 24] == autoc[] - ;[esp + 20] == lag - ;[esp + 16] ==

...v retrieving revision 1.10 diff -u Makefile --- Makefile 12 Feb 2009 03:21:56 -0000 1.10 +++ Makefile 25 Aug 2009 14:46:39 -0000 @@ -2,14 +2,14 @@ COMMENT= open video codec -DISTNAME= libtheora-1.0 +DISTNAME= libtheora-1.1beta3 CATEGORIES= multimedia MASTER_SITES= http://downloads.xiph.org/releases/theora/ EXTRACT_SUFX= .tar.bz2 SHARED_LIBS+= theora 3.1 SHARED_LIBS+= theoradec 1.0 -SHARED_LIBS+= theoraenc 1.1 +SHARED_LIBS+= theoraenc 1.2 HOMEPAGE= http://www.theora.org/ @@ -30,5 +30,8 @@ CONFIGURE_ARGS= --disable-examples CONFIGURE_ENV= ac_cv_prog_HAVE_DOXYGEN=false \ ac_cv_...

I'm seeing the following failures with "make check" (x86-32 linux): FAIL: test/CodeGen/X86/fold-mul-lohi.ll Failed with exit(1) at line 2 while running: llvm-as < test/CodeGen/X86/fold-mul-lohi.ll | llc -march=x86-64 | not grep lea leaq B, %rsi leaq A, %r8 leaq P, %rsi child process exited abnormally FAIL: