Displaying 3 results from an estimated 3 matches for "leaf_info".
2014 Dec 09
2
[LLVMdev] dmb ishld in AArch64
...tialized address
f90006b3 str x19, [x21,#8]
> Do you have preprocessed source or LLVM IR handy? (You can get a .i
> file from "clang -save-temps" for example).
The IR looks OK to me, the order is correct. I think the optimization is on machine code. The code is part of the insert_leaf_info function in net/ipv4/fib_trie.c
%37 = getelementptr inbounds %struct.leaf_info* %new, i64 0, i32 0, !dbg !10245
%38 = getelementptr inbounds %struct.leaf_info* %li.0.lcssa, i64 0, i32 0, !dbg !10245
tail call void @llvm.dbg.value(metadata !{%struct.hlist_node* %37}, i64 0, metadata !10246, m...
2014 Dec 09
4
[LLVMdev] dmb ishld in AArch64
Hi,
I got an optimization problem (O1, O2) regarding memory barrier “dmb ishld”
I find in the test/CodeGen/AArch64/intrinsics-memory-barrier.ll , it’s stated that memory access around DMB should not be reordered, but when compiling the Linux kernel, I found load/store in
static inline void hlist_add_before_rcu(struct hlist_node *n,
struct hlist_node *next)
{
n->pprev
2006 Jul 26
5
linux-2.6-xen.hg
Hi,
Is the http://xenbits.xensource.com/linux-2.6-xen.hg tree still being
updated? if not, what''s the preferred Linux tree to track that has all
of the Xen bits?
Thanks,
Muli
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel