search for: lea64r

Hi, I've been trying to teach LLVM that pointers are 128-bit long, which segfaults with some seemingly unrelated stacktrace when I try to take an address of a variable. Since stack saving and loading seems to work fine, I dare to assume the instruction causing problems there is leaq. Now I've done a search for leaq of the entire LLVM codebase with no success and I'd like to know which

...rInfo(); MachineInstr *plop = BuildMI(MF, DebugLoc(),tii.get(X86::JMP_4)).addMBB(origBB.at(1)); newEntry->push_back(plop); return false; } And here is the resulting code (it's a simple program with some 'if'): (null) BB#4 JMP_4 <BB#0> if.end BB#3 %RDI<def> = LEA64r %RIP, 1, %noreg, <ga:@.str2>, %noreg ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %AL<def> = MOV8ri 0 CALL64pcrel32 <ga:@printf>, <regmask>, %RSP<imp-use>, %AL<imp-use,kill>, %RDI<imp-use,kill>, %EAX<imp-def>...

...lways the case. For example: Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35) 308 %reg1051 = MOV64rr %reg1227<kill> 312 %reg1052 = MOV64rr %reg1228<kill> 316 %reg1053 = MOV64rr %reg1229<kill> 320 %reg1054 = MOV64rr %reg1230<kill> 324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0 328 %reg1135 = MOVSX64rr32 %reg1025 332 %reg1136 = MOV64rr %reg1135<kill> 336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead> 340 TEST64rr %reg1136<kill>, %reg1136, %EFLAGS<imp-def> 344 JNS mbb<file solve.f, line 23, in loop at depth 1, b...

...> Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35) > 308 %reg1051 = MOV64rr %reg1227<kill> > 312 %reg1052 = MOV64rr %reg1228<kill> > 316 %reg1053 = MOV64rr %reg1229<kill> > 320 %reg1054 = MOV64rr %reg1230<kill> > 324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0 > 328 %reg1135 = MOVSX64rr32 %reg1025 > 332 %reg1136 = MOV64rr %reg1135<kill> > 336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead> > 340 TEST64rr %reg1136<kill>, %reg1136, %EFLAGS<imp-def> > 344 JNS mbb<file solve.f, line...

...$src, > (MOVSDmr addr:$dst, FR64:$src))), imm:3) > > So I want to convert an unaligned vector store to a scalar store, a shuffle > and a scalar store. I got a little further with this: def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst), (MOVSDmr (ADD64ri8 (LEA64r addr:$dst), 8), (MOVPD2SDrr (SHUFPDrri (v2f64 VR128:$src), (v2f64 VR128:$src), 3)), (MOVSDmr addr:$dst, FR64: $src))>; Now tblgen (rightly) complains about MOVSDmr having too many operands. How do I specify the dependency MOVSD->SHUFPD->MOVSD? I'm a little nervous about the extra...

...don't see what is actually wrong here, and would like some help. Here is the output: # After Prologue/Epilogue Insertion & Frame Finalization # Machine code for function test_large: Post SSA Frame Objects: fi#0: size=40000, align=4, at location [SP-40000] BB#4: %R11<def> = LEA64r %RSP, 1, %noreg, -40040, %noreg CMP64rm %R11, %noreg, 1, %noreg, 40, %GS, %EFLAGS<imp-def> JA_1 <BB#0>, %EFLAGS<imp-use> Successors according to CFG: BB#3 BB#0 BB#3: Predecessors according to CFG: BB#4 %R10<def> = MOV64ri 40040 %R11&l...

I want to write a pattern that looks something like this: def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst), (MOVSDmr ADD64ri8(addr:$dst, imm:8), ( SHUFPDrri (VR128:$src, (MOVSDmr addr:$dst, FR64:$src))), imm:3) So I want to convert an unaligned vector store to a scalar store, a shuffle and a scalar store. There are several question I have: - Is the imm:3 syntax

...r of register copies when setting up parameters for a call: %reg1028<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0 %reg1029<def> = MOV32rm <fi#2>, 1, %reg0, 4, %reg0 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use> %reg1030<def> = LEA64r %RIP, 1, %reg0, <ga:@.str> %reg1031<def> = MOV8r0 %EFLAGS<imp-def,dead> %RDI<def> = MOV64rr %reg1030 %ESI<def> = MOV32rr %reg1028 %EDX<def> = MOV32rr %reg1029 %AL<def> = MOV8rr %reg1031 CALL64pcrel32 <ga:@printf>, %RDI, %ESI, %EDX, %AL, %RAX<...

On Tue, Jul 28, 2015 at 6:34 PM, Reid Kleckner <rnk at google.com> wrote: > On Tue, Jul 28, 2015 at 2:25 AM, John Kåre Alsaker > <john.mailinglists at gmail.com> wrote: >> >> On Tue, Jul 28, 2015 at 12:44 AM, Reid Kleckner <rnk at google.com> wrote: >> > Yeah, the function attributes section of LangRef is a reasonable place >> > to >>

...ad> = MOV32rr %EDI<kill> 12 %reg1025<def,dead> = MOV64rr %RSI<kill> 20 ADJCALLSTACKDOWN 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> 28 %reg1026<def> = MOV8ri 4 36 %reg1027<def> = FsFLD0SD 44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1> 52 %RDI<def> = MOV64rr %reg1028<kill> 60 %XMM0<def> = FsMOVAPDrr %reg1027 68 %XMM1<def> = FsMOVAPDrr %reg1027 76 %XMM2<def> = FsMOVAPDrr %reg1027 84 %XMM3<def> = FsMOVAPDrr %reg1027<kill> 92 %A...

...;<#1073741833>(d1880,b1874):u1887, u3755"<#1073741833>(d1865,b1874):u3752", u3756"<#1073741833>(d1861,b1874):u3753"] s1581: IMUL64rri8 [d1582<RAX>(+d3225,d1596,u1592):, d1583<EFLAGS>!(+d3225,d1595,):d1582, u1584<R12>(+d3220):] s1585: LEA64r [d1586<RSI>(+d3225,,u3772"):d1583, u1587<R15>(d776):, u1588<RAX>(d1582):] s1589: LEA64r [d1590<RDI>(+d3225,,u3771"):d1586, u1591<R14>(+d3142):u1455, u1592<RAX>(d1582):u1588] s1593: MOV32r0 [d1594<EAX>(d1582,,):, d1595<EFLAGS>!(d158...

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several

...; > 12 %reg1025<def,dead> = MOV64rr %RSI<kill> > 20 ADJCALLSTACKDOWN 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, > %ESP<imp-use> > 28 %reg1026<def> = MOV8ri 4 > 36 %reg1027<def> = FsFLD0SD > 44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1> > 52 %RDI<def> = MOV64rr %reg1028<kill> > 60 %XMM0<def> = FsMOVAPDrr %reg1027 > 68 %XMM1<def> = FsMOVAPDrr %reg1027 > 76 %XMM2<def> = FsMOVAPDrr %reg1027 > 84 %XMM3<def> = FsMOVAPDrr %reg10...

...;Two-Address instruction pass': MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%val] %vreg3<def> = MOV64ri64i32 4; GR64:%vreg3 %R8<def> = COPY %vreg3; GR64:%vreg3 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R8 %vreg4<def> = LEA64r <fi#0>, 1, %noreg, 0, %noreg; GR64:%vreg4 %R10<def> = COPY %vreg4; GR64:%vreg4 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R10 %vreg5<def> = MOV64ri64i32 3; GR64:%vreg5 %RDX<def> = COPY %vreg5; GR64:%vreg5 INLINEASM <es:> [si...

...:$src))), imm:3) >> >> So I want to convert an unaligned vector store to a scalar store, a >> shuffle >> and a scalar store. > > I got a little further with this: > > def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst), > (MOVSDmr (ADD64ri8 (LEA64r addr:$dst), 8), (MOVPD2SDrr > (SHUFPDrri > (v2f64 VR128:$src), (v2f64 VR128:$src), 3)), (MOVSDmr addr:$dst, FR64: > $src))>; > > Now tblgen (rightly) complains about MOVSDmr having too many > operands. How do > I specify the dependency MOVSD->SHUFPD->MOVSD? > &...

Hi Scott, That #1073741833 is a register mask. They are treated as aggregate registers (essentially sets of registers), so if it includes R9D and R11D, it will be treated as being aliased with both. These separate defs are there because they reach disjoint registers. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott

...; > Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35) > 308 %reg1051 = MOV64rr %reg1227<kill> > 312 %reg1052 = MOV64rr %reg1228<kill> > 316 %reg1053 = MOV64rr %reg1229<kill> > 320 %reg1054 = MOV64rr %reg1230<kill> > 324 %reg1055<dead> = LEA64r %reg1047, 1, %reg1053, 0 > 328 %reg1135 = MOVSX64rr32 %reg1025 > 332 %reg1136 = MOV64rr %reg1135<kill> > 336 %reg1136 = ADD64ri32 %reg1136, -4, %EFLAGS<imp-def,dead> > 340 TEST64rr %reg1136<kill>, %reg1136, %EFLAGS<imp-def> > 344 JNS mbb<file solve.f, line...

...f> = SUB64rr %reg1591, %reg1589, %EFLAGS<imp-def,dead> ; srcLine 0 2808 %reg1591<def> = IMUL64rr %reg1591, %reg1055, %EFLAGS<imp-def,dead> ; srcLine 0 2816 %reg1591<def> = ADD64rr %reg1591, %reg1579, %EFLAGS<imp-def,dead> ; srcLine 0 2820 %reg1198<def> = LEA64r %reg1591, 1, %reg1574, 0 ; srcLine 0 ##### %reg1591 gets spilled by linear scan with all of the uses in the sequence above reused by the "spltting" code in LiveIntervals. Note especially that %reg1591 is (correctly) identified at rematable (for the SUB64rr): ##### spilling(a): %re...

...<imp-use,kill> > Successors according to CFG: BB#3(12) BB#1(20) > > BB#1: > Predecessors according to CFG: BB#0 > %vreg9<def> = COPY %vreg1; GR64:%vreg9,%vreg1 > %vreg10<def> = COPY %vreg7; GR64:%vreg10,%vreg7 > %vreg0<def> = LEA64r %vreg7, 1, %noreg, 8, %noreg; GR64:%vreg0,%vreg7 > %vreg11<def> = COPY %vreg0; GR64:%vreg11,%vreg0 > Successors according to CFG: BB#2 > > BB#2: derived from LLVM BB %while.body > Predecessors according to CFG: BB#2 BB#1 > %vreg4<def> = COPY %vreg1...

...t;, 1, %NOREG, 1, 2 MOV8mi <fi#0> 1 %mreg(0) 1 2 8 FLDCW16m <fi#0>, 1, %NOREG, 0 FLDCW16m <fi#0> 1 %mreg(0) 0 12 ADJCALLSTACKDOWN 0, %ESP<imp-def>, %ESP<imp-use> ADJCALLSTACKDOWN 0 %mreg(25)<d> %mreg(25) 16 %reg1024 = MOV8r0 MOV8r0 %reg1024<d> 20 %reg1025 = LEA64r %NOREG, 1, %NOREG, <ga:initialized$$$CFE_id_cc092431_main> LEA64r %reg1025<d> %mreg(0) 1 %mreg(0) <ga:initialized$$$CFE_id_cc092431_main> 24 %RDI = MOV64rr %reg1025<kill> MOV64rr %mreg(78)<d> %reg1025 28 %AL<dead> = MOV8rr %reg1024<kill>, %EAX<imp-def&g...