Displaying 6 results from an estimated 6 matches for "ldxr".
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ldtr
2013 Mar 15
1
Re: [PATCH 6/9] tools: memshr: arm64 support
...quot;r" (v)
> : "cc");
> }
> +
> +#elif defined(__aarch64__)
> +
> +static inline void atomic_inc(uint32_t *v)
> +{
> + unsigned long tmp;
> + int result;
> +
> + asm volatile("// atomic_inc\n"
> +"1: ldxr %w0, [%3]\n"
> +" add %w0, %w0, #1\n"
> +" stxr %w1, %w0, [%3]\n"
> +" cbnz %w1, 1b"
> + : "=&r" (result), "=&r" (tmp), "+o" (v)
> + : "r" (v)
> +...
2017 May 30
3
[atomics][AArch64] Possible bug in cmpxchg lowering
...tly the AtomicExpandPass will lower the following IR:
define i1 @foo(i32* %obj, i32 %old, i32 %new) {
entry:
%v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release
acquire*_
%v1 = extractvalue { i32, i1 } %v0, 1
ret i1 %v1
}
to the equivalent of the following on AArch64:
_*ldxr w8, [x0]*_
cmp w8, w1
b.ne .LBB0_3
// BB#1: // %cmpxchg.trystore
stlxr w8, w2, [x0]
cbz w8, .LBB0_4
// BB#2: // %cmpxchg.failure
mov w0, wzr
ret
.LBB0_3:...
2020 Feb 10
3
atomic ops are optimized with incorrect semantics .
Hi All,
With the "https://gcc.godbolt.org/z/yBYTrd" case .
the atomic is converted to non atomic ops for x86 like
from
xchg dword ptr [100], eax
to
mov dword ptr [100], 1
the pass is responsible for this tranformation was instCombine
i.e InstCombiner::visitAtomicRMWInst
which converts the IR like
%0 = atomicrmw xchg i32* inttoptr (i64 100 to i32*), i32 1 monotonic
to
store
2013 Mar 15
22
[PATCH 00/09] arm: tools: build for arm64 and enable cross-compiling for both arm32 and arm64
The following patches shave some rough edges off the tools build system
to allow cross compiling for at least arm32 and arm64 based on the
Debian/Ubuntu multiarch infrastructure. They also add the necessary
fixes to build for arm64 (which I have only tried cross, not native).
I have posted some instructions on how to compile with these patches on
the wiki:
2013 Jan 23
132
[PATCH 00/45] initial arm v8 (64-bit) support
First off, Apologies for the massive patch series...
This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8
(AArch64) model. The kernel is the same one as I am currently using with
the 32 bit hypervisor
I haven''t yet tried starting a guest or anything super advanced like
that ;-). Also there is not real support for 64-bit domains at all,
although in one or two places I
2013 Feb 22
48
[PATCH v3 00/46] initial arm v8 (64-bit) support
This round implements all of the review comments from V2 and all patches
are now acked. Unless there are any objections I intend to apply later
this morning.
Ian.