search for: ldwsp

...d-line I use is: >> llc --regalloc=linearscan --march=xcore -f bugpoint-reduced- >> simplified.bc >> >> Any ideas about the reasons of this bug? >> >> Thanks, >> -Roman > It looks like it is trying to rematerialize a load from fixed stack > slot (LDWSP instruction). This has an implicit use of the SP > register which is non allocatable. > > rewriteInstructionsForSpills calls getReMatImplicitUse which returns > the SP register. This is then followed by a call to getInterval for > this register which fails. The attached patch c...

...at you can reproduce it. > > The command-line I use is: > llc --regalloc=linearscan --march=xcore -f bugpoint-reduced-simplified.bc > > Any ideas about the reasons of this bug? > > Thanks, > -Roman It looks like it is trying to rematerialize a load from fixed stack slot (LDWSP instruction). This has an implicit use of the SP register which is non allocatable. rewriteInstructionsForSpills calls getReMatImplicitUse which returns the SP register. This is then followed by a call to getInterval for this register which fails. The attached patch causes getReMatImplicitUse t...

...--march=xcore -f bugpoint-reduced- >>> simplified.bc >>> >>> Any ideas about the reasons of this bug? >>> >>> Thanks, >>> -Roman >>> >> It looks like it is trying to rematerialize a load from fixed stack >> slot (LDWSP instruction). This has an implicit use of the SP >> register which is non allocatable. >> >> rewriteInstructionsForSpills calls getReMatImplicitUse which returns >> the SP register. This is then followed by a call to getInterval for >> this register which fails....

Hi again, Now, after I fixed the graph coloring regalloc bug that was triggered by the ARM target, I continue testing and found another bug, this time on the XCore target. First I thought that it is again specific to my register allocator, but it seems to be trigerred also by LLVM's linearscan register allocator. I don't know if the XCore target is stable enough in LLVM, or may be I