Displaying 2 results from an estimated 2 matches for "ldwr".
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2010 Jul 28
3
[LLVMdev] Subregister coalescing
...s. Subregisters of same reg *never*
overlap.
Therefore, vector loads are lowered to scalar loads followed by a chain
of INSERT_VECTOR_ELTs. Then we select those to INSERT_SUBREG, everything
fine to that point.
Status before live analisys is (non-related instrs removed):
36 %reg16388<def> = LDWr %reg16384, 0; mem:LD4[<unknown>]
68 %reg16392<def> = INSERT_SUBREG %reg16392<undef>, %reg16388<kill>, 1
76 %reg16394<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>]
116 %reg16400<def> = MOVEV %reg16392<kill>
124 %reg16400<def> = INSERT_...
2010 Jul 28
0
[LLVMdev] Subregister coalescing
On Jul 28, 2010, at 12:25 PM, Carlos Sánchez de La Lama wrote:
> Which after register coalescing gets transformed into:
>
> 36 %reg16404:1<def> = LDWr %reg16384, 0; mem:LD4[<unknown>]
> 76 %reg16394<def> = LDWr %reg16386<kill>, 0; mem:LD4[<unknown>]
> 124 %reg16404<def> = INSERT_SUBREG %reg16404, %reg16394<kill>, 2
> 132 %reg16401<def> = LDWr %reg16390<kill>, 0; mem:LD4[<unknown>]
>...