search for: ldw_gp_v4

...o i32 %add = add i32 %conv2, %conv %add7 = add i32 %add, %conv5 %conv8 = trunc i32 %add7 to i8 store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the above load? ret void } At the point of enquiry I have the following (lowered) instructions: x3df7900: i32,ch = LDw_GP_V4 0x3df4c70, 0x3df5470<Mem:LD4[@q](tbaa=!"any pointer")> [ORD=8] [ID=6] // This is Load from q[0] 0x3df5470: ch = STb_GP_V4 0x3df5170, 0x3df4e70, 0x3d9c130<Mem:ST1[@s]> [ID=4] // This is a store to s Underlying Values: @q = common global i8* null, align 4 @s = common global i8...

...; wrote: > Eli, > >  I might not have answered your question fully/accurately... > > On my architecture, these _two_ loads are lowered to a single instruction: > > %3 = load i8** @q, align 4, !tbaa !2 > %4 = load i8* %3, align 1, !tbaa !0 > > Becomes > > i32,ch = LDw_GP_V4 0x3df4c70, 0x3df5470<Mem:LD4[@q](tbaa=!"any pointer") > > I guess what is happening, the alias properties of combined instruction are > not updated properly, and I am not sure if this is something I need to do, > or it is getting done "automatically" somewhere at...

Hi Jochen, > My llvm version is 3.0 release. > I have a module generated by clang. When I optimize it, I first add an > inlining pass (llvm::createFunctionInliningPass), then these passes: > - own FunctionPass > - llvm::createPromoteMemoryToRegisterPass > - llvm::createInstructionCombiningPass > - llvm::createDeadInstEliminationPass > - llvm::createDeadStoreEliminationPass

Hi! My llvm version is 3.0 release. I have a module generated by clang. When I optimize it, I first add an inlining pass (llvm::createFunctionInliningPass), then these passes: - own FunctionPass - llvm::createPromoteMemoryToRegisterPass - llvm::createInstructionCombiningPass - llvm::createDeadInstEliminationPass - llvm::createDeadStoreEliminationPass - new llvm::DominatorTree() - new

...(ins PredRegs:$src1, globaladdress:$global), >> + "if (!$src1.new) $dst=memuh(##$global)", >> + []>, >> + Requires<[HasV4T]>; >> + >> +let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in >> +def LDw_GP_V4 : LDInst<(outs IntRegs:$dst), >> + (ins globaladdress:$global), >> + "$dst=memw(#$global)", >> + []>, >> + Requires<[HasV4T]>; >> + >> +// if (Pv) Rt=memw(##global) >> +let mayLoad = 1, never...