search for: ldur

Displaying 6 results from an estimated 6 matches for "ldur".

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2015 Nov 23
1
[Aarch64 v2 05/18] Add Neon intrinsics for Silk noise shape quantization.
...e_shape_feedback_loop_neon: 000000000000004c ldr w9, [x0] 0000000000000050 cmp w3, #8 0000000000000054 b.ne 0x9c 0000000000000058 dup.4s v0, w9 000000000000005c ldr q1, [x1] 0000000000000060 ext.16b v0, v0, v1, #12 0000000000000064 ldur q1, [x1, #12] 0000000000000068 ldr q2, [x2] 000000000000006c sshll.4s v3, v2, #0 0000000000000070 sshll2.4s v2, v2, #0 0000000000000074 smull.2d v4, v0, v3 0000000000000078 smlal2.2d v4, v0, v3 000000000000007c smlal.2d...
2017 May 09
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...ction: switch statement lowered as cascaded-sequence-of-conditional-branches. Same issue causes MultiSource/Applications/sqlite3/sqlite3 (71%). Same issue causes MultiSource/Applications/lua/lua (46%). * SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of fneg: * FastISel: ldur d0, [x29,#-16] fneg d0, d0 stur d0, [x29,#-16] * GlobalISel: ldur d0, [x29,#-64] orr x8, xzr, #0x8000000000000000 fmov d1, x8 fsub d0, d1, d0 fmov x8, d0 stur x8, [x29,#-64] * MultiSource/Benchmarks/Prolangs-C++/city/city (74%): a call to memcpy for copying 4 bytes is present with...
2017 May 09
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...-conditional-branches. > Same issue causes MultiSource/Applications/sqlite3/sqlite3 (71%). > Same issue causes MultiSource/Applications/lua/lua (46%). > - SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of > fneg: > - FastISel: > ldur d0, [x29,#-16] > fneg d0, d0 > stur d0, [x29,#-16] > - GlobalISel: > ldur d0, [x29,#-64] > orr x8, xzr, #0x8000000000000000 > fmov d1, x8 > fsub d0, d1, d0 > fmov x8, d0 > stur x8, [x29,#-64]...
2015 Nov 20
2
[Aarch64 00/11] Patches to enable Aarch64
> On Nov 19, 2015, at 5:47 PM, John Ridges <jridges at masque.com> wrote: > > Any speedup from the intrinsics may just be swamped by the rest of the encode/decode process. But I think you really want SIG2WORD16 to be (vqmovns_s32(PSHR32((x), SIG_SHIFT))) Yes, you?re right. I forgot to run the vectors under qemu with my previous version (oh, the embarrassment!) Fixed forthcoming
2017 May 10
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...lowered as cascaded-sequence-of-conditional-branches. >> Same issue causes MultiSource/Applications/sqlite3/sqlite3 (71%). >> Same issue causes MultiSource/Applications/lua/lua (46%). >> SingleSource/Benchmarks/Misc/flops-2 (75%): Poor lowering of fneg: >> FastISel: >> ldur d0, [x29,#-16] >> fneg d0, d0 >> stur d0, [x29,#-16] >> GlobalISel: >> ldur d0, [x29,#-64] >> orr x8, xzr, #0x8000000000000000 >> fmov d1, x8 >> fsub d0, d1, d0 >> fmov x8, d0 >> stur x8, [x29,#-64] >> MultiSource/Benchmarks/Prolangs-C++/c...
2017 Apr 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Kristof, > On Apr 27, 2017, at 9:47 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > > Hi Quentin, > >> On 27 Apr 2017, at 00:48, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Hi Kristof, >> >>> On Apr 6, 2017, at 6:53 AM, Kristof Beyls <kristof.beyls at arm.com