Displaying 5 results from an estimated 5 matches for "ldtocl".
2017 Feb 09
2
Improving the split heuristics for the Greedy Register Allocator
...B <BB#3>
> 12 Successors according to CFG: BB#3(?%)
> 13
> 14 BB#1: derived from LLVM BB %if.end
> 15 Predecessors according to CFG: BB#0
> 16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
> 17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
> mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
> 18 %vreg8<def> = LWA 0, %vreg7;
> mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
> 19 %vreg9<def> = CMPLD %vreg8, %vreg15; CRRC:%vreg9...
2017 Jan 13
2
Improving the split heuristics for the Greedy Register Allocator
...rding to CFG: BB#0
11 B <BB#3>
12 Successors according to CFG: BB#3(?%)
13
14 BB#1: derived from LLVM BB %if.end
15 Predecessors according to CFG: BB#0
16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
18 %vreg8<def> = LWA 0, %vreg7;
mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
19 %vreg9<def> = CMPLD %vreg8, %vreg15; CRRC:%vreg9
G8RC:%vreg8,%vreg15...
2018 Dec 07
2
Should intrinsics llvm.eh.sjlj.setjmp be with isBarrier flag?
...function: main
basic block: %bb.2 for.body.lr.ph (0x100275437e8)
Content in block BB.2:
BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
%vreg2<def> = ADDIStocHA %X2, <ga:@env_sigill>;
G8RC_and_G8RC_NOX0:%vreg2
%vreg3<def> = LDtocL <ga:@env_sigill>, %vreg2<kill>; mem:LD8[GOT]
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg2
%vreg4<def> = EH_SjLj_SetJmp64 %vreg3<kill>, %CTR8<imp-def,dead>;
GPRC:%vreg4 G8RC:%vreg3
Currently Powerpc sets EH_SjLj_SetJmp64 with flag isBarrier. But it is also
a fall-thro...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg18<def> = DIVD %vreg16, %vreg17;
G8RC:%vreg18,%vreg16,%vreg17
464B %vreg21<def> = DIVD %vreg19, %vreg20;
G8RC:%vreg21,%vreg19,%vreg20
472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>;
G8RC_and_G8RC_NOX0:%vreg5
480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>;
mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5
504B %X3<def> = LI8 0
512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds
([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4
G8RC_and_G8RC_NOX0:%vreg6
520B...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...= DIVD %vreg16, %vreg17; G8RC:%vreg18,%vreg16,%vreg17
>> 464B %vreg21<def> = DIVD %vreg19, %vreg20; G8RC:%vreg21,%vreg19,%vreg20
>> 472B %vreg5<def> = ADDIStocHA %X2, <ga:@A>; G8RC_and_G8RC_NOX0:%vreg5
>> 480B %vreg6<def> = LDtocL <ga:@A>, %vreg5, %X2<imp-use>; mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg6,%vreg5
>> 504B %X3<def> = LI8 0
>> 512B STD %vreg4, 0, %vreg6; mem:ST8[getelementptr inbounds ([100 x i64], [100 x i64]* @A, i64 0, i64 0)](tbaa=!4) G8RC:%vreg4 G8RC_and_G8RC_NO...