Displaying 3 results from an estimated 3 matches for "ldststdu".
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ldststdcx
2013 Oct 01
0
[LLVMdev] Post Increment Indirect Move Instructions
...re is a constraint that some input operand must be the same as some output operand. For example, the PowerPC backend has a pre-increment store encoded like this:
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
"stdux $rS, $dst", LdStSTDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">;
}
def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
(STDUX $rS, $ptrreg, $ptroff)>;
Note that the instruction has a pseudo-output operand $ea_res whic...
2013 Oct 08
1
[LLVMdev] Post Increment Indirect Move Instructions
...int that some input operand must be the same as some output operand. For example, the PowerPC backend has a pre-increment store encoded like this:
>
> def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
> "stdux $rS, $dst", LdStSTDU, []>,
> RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">;
> }
>
> def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
> (STDUX $rS, $ptrreg, $ptroff)>;
>
> Note that the instruction has a...
2013 Oct 01
2
[LLVMdev] Post Increment Indirect Move Instructions
Hi Hal,
Our Architecture has indirect move instruction which increments the
pointer implicitly and the target only has i8 type values. So the load
of i16 will be converted to two i8 target loads wherein after the first
load instruction, the pointer to the first i8 address will automatically
increment to point to the next i8 value. So the post increment nature is
in the Target. A normal