search for: ldst

...000000; > + break; > case FILE_MEMORY_SHARED: > code[0] = 0x00000002; > if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) > @@ -1800,7 +1815,8 @@ CodeEmitterGK110::emitMOV(const Instruction *i) > static inline bool > uses64bitAddress(const Instruction *ldst) > { > - return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && > + return (ldst->src(0).getFile() == FILE_MEMORY_BUFFER || > + ldst->src(0).getFile() == FILE_MEMORY_GLOBAL) && > ldst->src(0).isIndirect(0) && > ld...

...> case FILE_MEMORY_LOCAL: code[1] = 0x7a000000; code[0] = 0x00000002; > break; > case FILE_MEMORY_SHARED: > code[0] = 0x00000002; > @@ -1800,7 +1800,7 @@ CodeEmitterGK110::emitMOV(const Instruction *i) > static inline bool > uses64bitAddress(const Instruction *ldst) > { > - return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL && > + return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && > ldst->src(0).isIndirect(0) && > ldst->getIndirect(0, 0)->reg.size == 8; > } > @@ -1862,7 +1862...

tgsi_default_instruction_memory / tgsi_build_instruction_memory were returning uninitialized memory for tgsi_instruction_memory.Texture and tgsi_instruction_memory.Format. Note 0 means not set, and thus is a correct default initializer for these. Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory") Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>

...0000; code[0] = 0x00000000; break; case FILE_MEMORY_LOCAL: code[1] = 0x7a000000; code[0] = 0x00000002; break; case FILE_MEMORY_SHARED: code[0] = 0x00000002; @@ -1800,7 +1800,7 @@ CodeEmitterGK110::emitMOV(const Instruction *i) static inline bool uses64bitAddress(const Instruction *ldst) { - return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL && + return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && ldst->src(0).isIndirect(0) && ldst->getIndirect(0, 0)->reg.size == 8; } @@ -1862,7 +1862,7 @@ CodeEmitterGK110::emitCCTL(co...

...e[0] = 0x00000002; + code[1] = 0x7a000000; + break; case FILE_MEMORY_SHARED: code[0] = 0x00000002; if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) @@ -1800,7 +1815,8 @@ CodeEmitterGK110::emitMOV(const Instruction *i) static inline bool uses64bitAddress(const Instruction *ldst) { - return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && + return (ldst->src(0).getFile() == FILE_MEMORY_BUFFER || + ldst->src(0).getFile() == FILE_MEMORY_GLOBAL) && ldst->src(0).isIndirect(0) && ldst->getIndirect(0, 0)->reg....

...CAL: code[1] = 0x7a000000; code[0] = 0x00000002; >> break; >> case FILE_MEMORY_SHARED: >> code[0] = 0x00000002; >> @@ -1800,7 +1800,7 @@ CodeEmitterGK110::emitMOV(const Instruction *i) >> static inline bool >> uses64bitAddress(const Instruction *ldst) >> { >> - return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL && >> + return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && >> ldst->src(0).isIndirect(0) && >> ldst->getIndirect(0, 0)->reg.size == 8; >&g...

...k; >> case FILE_MEMORY_SHARED: >> code[0] = 0x00000002; >> if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) >> @@ -1800,7 +1815,8 @@ CodeEmitterGK110::emitMOV(const Instruction *i) >> static inline bool >> uses64bitAddress(const Instruction *ldst) >> { >> - return ldst->src(0).getFile() == FILE_MEMORY_BUFFER && >> + return (ldst->src(0).getFile() == FILE_MEMORY_BUFFER || >> + ldst->src(0).getFile() == FILE_MEMORY_GLOBAL) && >> ldst->src(0).isIndirect(0) &&...

...to look at the generated code. The code from gcc matches almost exactly what is listed in the ABI document. However, LLVM seems very different. I don't see -fPIC has having any impact with mcmodel=large. Thanks John For example, static int src; // Lsrc: .long static int dst; // Ldst: .long extern int *dptr; // .extern dptr void DataLoadAndStore() { // Large Memory Model code sequences from AMD64 abi // Figure 3.22: Position-Independent Global Data Load and Store // // Assume that %r15 has been loaded with GOT address by // function prologue. // movabs $L...

...in inline asm: '/* result: ${0:c} */' Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll ** error: invalid operand in inline asm: '.foo_directive ${0:c}:${1:c}' Also, Gabor, there is one left-over assembly file that must be manually removed: CodeGen/ARM64/indexed-vector-ldst-2.s cheers, --renato

...to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is dispatched to AGQ and a writeback micro-op which is dispatched to FPQ. The AGQ micro-op is issued to a four-cycle latency pipeline called LDST. Three cycles after issue, the LDST pipeline wakes up the FPQ micro-op, which writes the result of the load back to the register file. Is it possible to use other instructions already scheduled for the same cycle as part of the evaluation of a SchedPredicate in a SchedVariant? I've got a class...

...64-stur.ll > llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll > llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll > llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll > llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll > llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll > llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll > llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll > llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll > llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll > llvm/trunk/test/CodeGen/AArch64/merges...

This is a bad bug as reported by Robin Hankin, it is still in "R-patched" ... ##- From: Robin Hankin <r.hankin@auckland.ac.nz> ##- To: r-help@stat.math.ethz.ch ##- Subject: [R] possum sleeping: thanks and fisher.test() FEXACT error ##- Date: Thu, 13 Jun 2002 16:46:26 +1200 ## ..... ## Example slighlty modified (MM) d4 <- matrix(c(0, 0, 0, 0, 0, 0, 3, 0, 1, 0, 0, 0, 0, 0,

.../test/CodeGen/AArch64/arm64-stur.ll llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll llvm/trunk/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll...

...llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll >> llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll >> llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll >> llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll >> llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll >> llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll >> llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll >> llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll >> llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll >> llvm/trunk/test/Co...

...t/CodeGen/AArch64/arm64-virtual_base.ll >>> llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll >>> llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll >>> llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll >>> llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll >>> llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll >>> llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll >>> llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll >>> llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll >>>...

.../test/CodeGen/AArch64/arm64-stur.ll llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll llvm/trunk/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll...

.../test/CodeGen/AArch64/arm64-stur.ll llvm/trunk/test/CodeGen/AArch64/arm64-virtual_base.ll llvm/trunk/test/CodeGen/AArch64/fast-isel-memcpy.ll llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll llvm/trunk/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll llvm/trunk/test/CodeGen/AArch64/ldst-paired-aliasing.ll llvm/trunk/test/CodeGen/AArch64/ldst-zero.ll llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll llvm/trunk/test/CodeGen/AArch64/memcpy-f128.ll llvm/trunk/test/CodeGen/AArch64/merge-store-dependency.ll llvm/trunk/test/CodeGen/AArch64/mergestores_noimplicitfloat.ll...

...to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is dispatched to AGQ and a writeback micro-op which is dispatched to FPQ. The AGQ micro-op is issued to a four-cycle latency pipeline called LDST. Three cycles after issue, the LDST pipeline wakes up the FPQ micro-op, which writes the result of the load back to the register file. This question illustrates the primary difference between the per-operand machine model and the itinerary. The itinerary directly models the stages of each pipeline...