Displaying 6 results from an estimated 6 matches for "ldrsh".
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2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...@ r4 = mem, r5 = ord
cmp r5, #10
beq .order_10
cmp r5, #8
beq .order_8
ldmia sp!, { r4-r11, pc } @ Mon-supported order, return
@ TODO: try using direct form 1 filtering
.order_8:
ldmia r4, { r5-r12 } @ r5-r12 = mem[0..7]
0:
ldrsh r14, [r0], #2
add r5, r5, #4096 @ Rounding constant
str r0, [sp,#-4]! @ push r0
add r14, r14, r5, asr #13 @ (mem[0] + 4096) >> 13 + x[i]
mov r5, #0x7f00
orr r5, r5, #0xff @ r5 = 32767
cmp r14, r5
movgt r14...
2013 Jan 23
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...d llc -O3 -march=arm -regalloc=greedy, and here is the code that is generated for the loop body (and two instructions that set a loop-invariant mask beforehand), with some comments of mine:
>
> mov r12, #255
> orr r12, r12, #65280
> LBB1_1:
> ldrsh r3, [r1] # loads a short that is sign-extended to 32 bits
> mov r4, lr
> cmp r3, #2048
> bge .LBB1_3
> and r4, r3, r12 # mask with 0xffff to convert to short again
> lsl r4, r4, #16 #...
2013 Jan 24
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...arm -regalloc=greedy, and here is the code that is generated for the loop body (and two instructions that set a loop-invariant mask beforehand), with some comments of mine:
>>
>> mov r12, #255
>> orr r12, r12, #65280
>> LBB1_1:
>> ldrsh r3, [r1] # loads a short that is sign-extended to 32 bits
>> mov r4, lr
>> cmp r3, #2048
>> bge .LBB1_3
>> and r4, r3, r12 # mask with 0xffff to convert to short again
>> lsl r4, r4,...
2007 Dec 12
2
Speex crashing on ARM with assembler optimization enabled.
...speex.so.1
#3 0x40036c84 in speex_encode_int () from ./libspeex.so.1
#4 0x00008d68 in main ()
(gdb) disassemble
Dump of assembler code for function open_loop_nbest_pitch:
... skipped...
0x40030300 <open_loop_nbest_pitch+620>: add r0, r3, r8
0x40030304 <open_loop_nbest_pitch+624>: ldrsh r3, [r0]
0x40030308 <open_loop_nbest_pitch+628>: mov r3, r3, lsl #1
0x4003030c <open_loop_nbest_pitch+632>: strh r3, [r0], #2
0x40030310 <open_loop_nbest_pitch+636>: add r6, r6, #1 ; 0x1
0x40030314 <open_loop_nbest_pitch+640>: cmp r6, r7
0x40030318 <...
2007 Dec 12
2
Speex crashing on ARM with assembler optimization enabled.
Hi,
I'm trying to get speex working on an ARM board (ARM926EJ-Sid(wb) core,
ARM 5TE architecture) and getting segfaults if build with "--enable-fixed-point
--enable-arm5e-asm" options. If I use just "--enable-fixed-point", then
it runs fine, but once I add "--enable-arm5e-asm" it start crashing
(I use testenc to test it).
Further investigation showed, that it
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
> On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
>> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are