Displaying 6 results from an estimated 6 matches for "ldrrs".
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
...def>;
> Bcc <BB#9>, pred:0, pred:%CPSR<kill>;
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg; mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg; mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRBi12 %R6, %R7<kill>, 0, pred:14, pred:%noreg; mem:ST1[%21](align=4)
>...
2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
...<BB#9>, pred:0, pred:%CPSR<kill>;
>
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg;
> mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg;
> mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRBi12 %R6, %R7<kill>, 0, pred:14, pred:%noreg; mem:ST1[%21](...
2018 Apr 09
2
How to get the case value from Machine Instruction
...14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb.6 %bb.1
%bb.1: derived from LLVM BB %1
Predecessors according to CFG: %bb.0
%1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg
%2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable]
BR_JTr killed %2, %jump-table.0
Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%)
%bb.2: derived from LLVM BB %2
Predecessors according to CFG: %bb.1
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = ADDri %r0, 11, 14, %nor...
2018 Apr 09
0
How to get the case value from Machine Instruction
...eg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb.6 %bb.1
%bb.1: derived from LLVM BB %1
Predecessors according to CFG: %bb.0
%1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg
%2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable]
BR_JTr killed %2, %jump-table.0
Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%)
%bb.2: derived from LLVM BB %2
Predecessors according to CFG: %bb.1
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = ADDri %r0, 11, 1...
2018 Apr 10
1
How to get the case value from Machine Instruction
...eg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb.6 %bb.1
%bb.1: derived from LLVM BB %1
Predecessors according to CFG: %bb.0
%1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg
%2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable]
BR_JTr killed %2, %jump-table.0
Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%)
%bb.2: derived from LLVM BB %2
Predecessors according to CFG: %bb.1
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = ADDri %r0, 11, 1...
2018 Apr 09
0
How to get the case value from Machine Instruction
...14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %cpsr
STRi12 %r0, %stack.3, 14, %noreg
Bcc %bb.6, 8, %cpsr
Successors according to CFG: %bb.6 %bb.1
%bb.1: derived from LLVM BB %1
Predecessors according to CFG: %bb.0
%1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg
%2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable]
BR_JTr killed %2, %jump-table.0
Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%)
%bb.2: derived from LLVM BB %2
Predecessors according to CFG: %bb.1
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = ADDri %r0, 11, 14, %nor...