Displaying 3 results from an estimated 3 matches for "ldresult".
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hdresult
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
...ISD::LoadExtType ExtType = LD->getExtensionType();
if (LD->getExtensionType() == ISD::ZEXTLOAD) {
DEBUG(errs() << "ZEXTLOAD\n");
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
DebugLoc dl = Op.getNode()->getDebugLoc();
SDValue LdResult = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32,
Chain, Ptr, LD->getPointerInfo(),
MVT::i32,
LD->isVolatile(), LD->isNonTemporal(),
LD->getAlignment());
Chain = LdResult.get...
2008 Nov 11
0
[LLVMdev] Load/Store issues: tablegen/customization?
On Nov 10, 2008, at 1:20 PM, Daniel M Gessel wrote:
> I've been running into two issues with load/store handling:
>
> (1) is that tablegen doesn't seem to handle the two predicates that
> get attached to my instructions. The first is the predicate in
> TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The
> second is my identification of the load as
2008 Nov 10
2
[LLVMdev] Load/Store issues: tablegen/customization?
I've been running into two issues with load/store handling:
(1) is that tablegen doesn't seem to handle the two predicates that
get attached to my instructions. The first is the predicate in
TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The
second is my identification of the load as having a particular address
space (need different instructions for different