search for: ldnp

...ort non-temporal instructions and require > barriers such as DMB nshld to order loads and DMB nshst to order stores. > > > > Even ARM's address-dependency rule (a.k.a. the ill-fated > std::memory_order_consume) fails to hold with non-temporals: > > LDR X0, [X3] > > LDNP X2, X1, [X0] // X0 may not be loaded when the instruction executes! > > > > What exactly do you mean by ‘X0 may not be loaded’ in your example here? > If you mean that the LDNP > > could start executing with the value of X0 from before the LDR, e.g. > initially X0=0x100, th...

...x.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html > > > > Which is correct? > > FWIW, I agree with John here. The example I'd give for the unexpected > behaviour allowed in the spec is: > > .Lwait_for_data: > ldr x0, [x3] > cbz x0, .Lwait_for_data > ldnp x2, x1, [x0] > > where another thread first writes to a buffer then tells us where that > buffer is. For a normal ldp, the address dependency rule means we > don't need a barrier or acquiring load to ensure we see the real data > in the buffer. For ldnp, we would need a barrier t...

...gt; Which is correct? >>> >>> FWIW, I agree with John here. The example I'd give for the unexpected >>> behaviour allowed in the spec is: >>> >>> .Lwait_for_data: >>> ldr x0, [x3] >>> cbz x0, .Lwait_for_data >>> ldnp x2, x1, [x0] >>> >>> where another thread first writes to a buffer then tells us where that >>> buffer is. For a normal ldp, the address dependency rule means we >>> don't need a barrier or acquiring load to ensure we see the real data >>> in the buf...

...rchitectures?* Architectures such as ARMv8 support non-temporal instructions and require barriers such as DMB nshld to order loads and DMB nshst to order stores. Even ARM's address-dependency rule (a.k.a. the ill-fated std::memory_order_consume) fails to hold with non-temporals: LDR X0, [X3] LDNP X2, X1, [X0] // X0 may not be loaded when the instruction executes! *Who uses non-temporals anyways?* That's an awfully personal question! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160112/d6d189...

...FWIW, I agree with John here. The example I'd give for the unexpected >>>>> behaviour allowed in the spec is: >>>>> >>>>> .Lwait_for_data: >>>>> ldr x0, [x3] >>>>> cbz x0, .Lwait_for_data >>>>> ldnp x2, x1, [x0] >>>>> >>>>> where another thread first writes to a buffer then tells us where that >>>>> buffer is. For a normal ldp, the address dependency rule means we >>>>> don't need a barrier or acquiring load to ensure we see the r...

...arriers such as DMB nshld to order loads and DMB nshst to > > order stores. > > > Even ARM's address-dependency rule (a.k.a. the ill-fated > > std::memory_order_consume ) fails to hold with non-temporals: > > > > LDR X0, [X3] > > > > > > LDNP X2, X1, [X0] // X0 may not be loaded when the instruction > > > executes! > > > > > Who uses non-temporals anyways? > > > That's an awfully personal question! > > _______________________________________________ > LLVM Developers mailing list > l...

On 01/14/2016 04:05 PM, Hans Boehm via llvm-dev wrote: > > > On Thu, Jan 14, 2016 at 1:37 PM, JF Bastien <jfb at google.com > <mailto:jfb at google.com>> wrote: > > On Thu, Jan 14, 2016 at 1:35 PM, David Majnemer > <david.majnemer at gmail.com <mailto:david.majnemer at gmail.com>> wrote: > > > > On Thu, Jan 14, 2016 at 1:13