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...how LDR is defined: def addrmodepc : Operand<i32>, ComplexPattern<i32, 2, "SelectAddrModePC", []> { let PrintMethod = "printAddrModePCOperand"; let MIOperandInfo = (ops GPR, i32imm); } def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, "ldr", "\t$dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; It's using addrmodepc, which is a ComplexPattern. The TableGen code cannot handle resetting the memoperands if it's dealing with a ComplexPattern. There'...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,

...ef addrmodepc : Operand<i32>, > ComplexPattern<i32, 2, "SelectAddrModePC", []> { > let PrintMethod = "printAddrModePCOperand"; > let MIOperandInfo = (ops GPR, i32imm); > } > def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, > IIC_iLoadr, > "ldr", "\t$dst, $addr", > [(set GPR:$dst, (load addrmode2:$addr))]>; > > It's using addrmodepc, which is a ComplexPattern. The TableGen code cannot > handle resetting the memoperands if it's dealing with a...

Hi All, I started to work on code-size improvements on ARM target by comparing GCC and LLVM generated code. My first candidate was switch-case lowering. I also created a Bugzilla issue for this topic: https://bugs.llvm.org/show_bug.cgi?id=34902 The full example code and the generated assembly for GCC and for LLVM is in the Bugzilla issue. My first idea was to simplify the following