search for: lddw

> This is contradictory: on a little-endian processor, the address for > loading a 64-bit value is same as the address of the low word. Are > you sure you're modeling the semantics of your lddw and stddw > instructions correctly? ... I thought so until now. Because I implemented stdw (store doubleword) completely analogous to lddw: Just print out stdw with the given pointer and the register pair, just like lddw. (This seems obvious.) Well, ****. I just read the documentation very ca...

...r::ReduceLoadWidth. The error is introduced because the offset is not calculated correctly. The first problem is that the pointer I get for loading does not point to the address of the low word, but to the address of the high word. The second problem is that this is apparently correct as long as lddw is used instead of ldw. Do you have any ideas on this? (The third problem is that the creation of the pointer is not my doing. I'm just extending our backend to support i64 additionally (instead of just i32 and smaller). Doing this turns out to be trickier than expected.) Cheers, Johannes

...ter I get for loading does not point > to the address of the low word, but to the address of the high word. This is contradictory: on a little-endian processor, the address for loading a 64-bit value is same as the address of the low word. Are you sure you're modeling the semantics of your lddw and stddw instructions correctly? -Eli

...n the high bits being loaded into the return register, instead of the low bits, as should happen with truncate. Details: i64 's are stored in two adjacent 32 bit registers. So the store happens like this: "stddw 0xBBBBBBBB33333333, *$ptr" and the load should happen like this: "lddw *$ptr, A5:A4" . It is easy to see that if "ldw *$ptr, A4" is printed, then the high bits will be loaded into A4. Something like this would be correct just like the lddw variant: "ldw *-$ptr(4), A4" Is there a way to change this behavior (that (trunc (load doubleword)) is...

...o the return > register, instead of the low bits, as should happen with truncate. > > Details: i64 's are stored in two adjacent 32 bit registers. So the > store happens like this: > "stddw 0xBBBBBBBB33333333, *$ptr" > and the load should happen like this: > "lddw *$ptr, A5:A4" > . It is easy to see that if > "ldw *$ptr, A4" > is printed, then the high bits will be loaded into A4. Something like > this would be correct just like the lddw variant: > "ldw *-$ptr(4), A4" > > Is there a way to change this behavior (t...

...m getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a load with displacement instruction of the form "load reg, [reg_addr+<offs>]...

...ier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr:$src))]>; > > This is just a load with displacement instruction of the form "load reg...

...rlyclobber > constraint to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > > let canFoldAsLoad = 1, > > isReMaterializable = 1, > > Constraints = "@earlyclobber $dst" in > > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > > (ins memri:$src), > > "lddw\t$dst, $src", > > [(set DREGS:$dst, (load addr:$src))]>; > > > > This is just a load with displacement instruction of...

...nt to some instructions where the src and dest regs can't be the >> same. The offending instruction pattern is this one: >> > >> > let canFoldAsLoad = 1, >> > isReMaterializable = 1, >> > Constraints = "@earlyclobber $dst" in >> > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), >> > (ins memri:$src), >> > "lddw\t$dst, $src", >> > [(set DREGS:$dst, (load addr:$src))]>; >> > >> > This is just a load with displac...