Displaying 15 results from an estimated 15 matches for "ldarx".
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2008 Jul 08
3
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...nserter = 1 in {
> + let Uses = [CR0] in {
> + let Uses = [R0] in
> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>
> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> expanded like this later:
>
> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
> + .addReg(ptrA).addReg(ptrB);
> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
> + .addReg(incr).addReg(dest);
> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> + .addReg(PPC::R0).addReg(ptrA).addReg(pt...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...let Uses = [CR0] in {
>> + let Uses = [R0] in
>> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>>
>> The "let Uses = [R0]" is not needed. The pseudo instruction will be
>> expanded like this later:
>>
>> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
>> + .addReg(ptrA).addReg(ptrB);
>> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
>> + .addReg(incr).addReg(dest);
>> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
>> + .addReg(PPC::R0).ad...
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======================================
--- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy)
@@ -116,23 +116,35 @@
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
(BL8_ELF texternalsym:$dst)>;
-// Atomic operations.
-def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label),
- "\nLa${label}_entry:\n\tldarx $rD, $ptr",
- [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
+// Atomic operations
+let usesCustomDAGSchedInserter = 1 in {
+ let Uses = [CR0] in {...
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======================================
--- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy)
@@ -116,23 +116,34 @@
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
(BL8_ELF texternalsym:$dst)>;
-// Atomic operations.
-def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label),
- "\nLa${label}_entry:\n\tldarx $rD, $ptr",
- [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
+// Atomic operations
+let usesCustomDAGSchedInserter = 1 in {
+ let Uses = [CR0] in {...
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...; + let Uses = [R0] in
> >> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
> >>
> >> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> >> expanded like this later:
> >>
> >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
> >> + .addReg(ptrA).addReg(ptrB);
> >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
> >> + .addReg(incr).addReg(dest);
> >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
> >> +...
2008 Jul 04
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...e one comment:
+let usesCustomDAGSchedInserter = 1 in {
+ let Uses = [CR0] in {
+ let Uses = [R0] in
+ def ATOMIC_LOAD_ADD_I32 : Pseudo<
The "let Uses = [R0]" is not needed. The pseudo instruction will be
expanded like this later:
+ BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ .addReg(ptrA).addReg(ptrB);
+ BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0)
+ .addReg(incr).addReg(dest);
+ BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ .addReg(PPC::R0).addReg(ptrA).addReg(ptrB);
The second instruct...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======================================
--- lib/Target/PowerPC/PPCInstr64Bit.td (revision 53464)
+++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy)
@@ -116,23 +116,34 @@
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
(BL8_ELF texternalsym:$dst)>;
-// Atomic operations.
-def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label),
- "\nLa${label}_entry:\n\tldarx $rD, $ptr",
- [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
+// Atomic operations
+let usesCustomDAGSchedInserter = 1 in {
+ let Uses = [CR0] in {...
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36
2008 Jul 10
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Just cast both values to const TargetRegisterClass*.
Evan
On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> Evan Cheng wrote:
>> How about?
>>
>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
>> &PPC:G8RCRegClass;
>> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
>
> I tried something like that yesterday:
>
> const
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote:
> How about?
>
> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> &PPC:G8RCRegClass;
> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
I tried something like that yesterday:
const TargetRegisterClass *RC =
is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass;
but I kept getting this error no matter how I arranged it:
2008 Jun 30
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
You need to insert new basic blocks and update CFG to accomplish this.
There is a hackish way to do this right now. Add a pseudo instruction
to represent this operation and mark it usesCustomDAGSchedInserter.
This means the intrinsic is mapped to a single (pseudo) node. But it
is then expanded into instructions that can span multiple basic
blocks. See
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======================================
--- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy)
@@ -116,23 +116,34 @@
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
(BL8_ELF texternalsym:$dst)>;
-// Atomic operations.
-def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label),
- "\nLa${label}_entry:\n\tldarx $rD, $ptr",
- [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
+// Atomic operations
+let usesCustomDAGSchedInserter = 1 in {
+ let Uses = [CR0] in {...
2008 Jun 30
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Chris Lattner wrote:
> On Jun 27, 2008, at 8:27 AM, Gary Benson wrote:
> > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:
> > $label),
> > "cmpw $rA, $rB\n\tbne- La${label}_exit",
> > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:
> > $label)]>;
> > }
> >
> > ...and
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...erPC/atomic-2.ll
index e56a779..261335e 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -11,7 +11,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
define i64 @exchange_and_cmp(i64* %mem) nounwind {
; CHECK-LABEL: exchange_and_cmp:
; CHECK: ldarx
- %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
+ %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
; CHECK: stdcx.
; CHECK: stdcx.
ret i64 %tmp
diff --git a/test/CodeGen/SPARC/atomics.ll b/test/CodeGen/SPARC/atomics.ll
index b10336c..4e3e7ae 100644
--- a/test/CodeGen/SPARC/atomi...