search for: ld4ln_wb_h_regist

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[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
2013 Nov 28
2
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...Arch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: { > switch (Opc) { > case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: > - TransferBytes = 3; break; > + TransferBytes = 4; break; > case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: > - TransferBytes = 6; break; > + TransferBytes = 8; break; > case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: > - TransferBytes = 12; break; > + TransferBytes = 16; break; > case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_W...
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
2013 Nov 28
0
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...ixed: case AArch64::LD4LN_WB_D_register: { >> switch (Opc) { >> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: >> - TransferBytes = 3; break; >> + TransferBytes = 4; break; >> case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: >> - TransferBytes = 6; break; >> + TransferBytes = 8; break; >> case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: >> - TransferBytes = 12; break; >> + TransferBytes = 16; break; >> case AArch64::LD4LN_WB_D_fixe...
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
2013 Nov 28
1
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...LN_WB_D_register: { >>> switch (Opc) { >>> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: >>> - TransferBytes = 3; break; >>> + TransferBytes = 4; break; >>> case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: >>> - TransferBytes = 6; break; >>> + TransferBytes = 8; break; >>> case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: >>> - TransferBytes = 12; break; >>> + TransferBytes = 16; break; >>> cas...