Displaying 3 results from an estimated 3 matches for "ld4ln_wb_d_fix".
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ld4ln_wb_d_fixed
2013 Nov 28
2
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...==================
> --- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed Nov 27 19:07:45 2013
> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
> switch (Opc) {
> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
> - TransferBytes = 3; break;
> + TransferBytes = 4; break;
> case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
&...
2013 Nov 28
0
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...vm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed
>> Nov 27 19:07:45 2013
>> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
>> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
>> switch (Opc) {
>> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
>> - TransferBytes = 3; break;
>> + TransferBytes = 4; break;
>> case AArch64::LD4LN_WB_H_fixed: case AArch64::LD...
2013 Nov 28
1
[LLVMdev] [llvm] r195903 - AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
...Arch64/Disassembler/AArch64Disassembler.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed
>>> Nov 27 19:07:45 2013
>>> @@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
>>> case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
>>> switch (Opc) {
>>> case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
>>> - TransferBytes = 3; break;
>>> + TransferBytes = 4; break;
>>> case AArch64::LD4LN_WB_H_...