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I am not sure what you are looking to do. Please provide a mark up example. Evan On Oct 28, 2008, at 11:00 AM, Villmow, Micah wrote: > Is there currently a way to use a pattern inside of another pattern? > > Micah Villmow > Systems Engineer > Advanced Technology & Performance > Advanced Micro Devices Inc. > 4555 Great America Pkwy, > Santa Clara, CA. 95054 > P:

...subtraction // a - b ==> a + (-b) def ISUB : Pat<(sub GPRI32:$src0, GPRI32:$src1), (IADD GPRI32:$src0, (INEGATE GPRI32:$src1))>; I am attemping to do 64 bit integer shifts and using the following pattern: def LSHL : Pat<(shl GPRI64:$src0, GPRI32:$src1), (LCREATE (ISHL (LLO GPRI64:$src0), GPRI32:$src1), (IOR (ISHL (LHI GPRI64:$src0), GPRI32:$src1), (IOR (USHR (LLO GPRI64:$src0), (IADD (LOADCONST_i32 32), (INEGATE GPRI32:$src1))), (USHR (LLO GPRI64:$src0), (IADD GPRI32:$src1, (LOADCONST_i32 -32))))))>; However, I have two adds that I could...

Is there currently a way to use a pattern inside of another pattern? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL:

...t; > when lowering a specific instruction within the TargetLowering? [Villmow, Micah] Have you tried using a tablegen pattern here? I find it is easier for simple conversions like this than using C++ code. For example our backend does this with: def uitoli64rr:Pat < (i64 (zext GPRI32:$src)), (LCREATEi64rr GPRI32:$src, (LOADCONSTi32 0)) >; Where LCREATE is a machine instruction that does similar to ISD::BUILD_PAIR from two i32's and outputs a i64. > > Any hints are highly welcome! > > Ciao, Fabian > _______________________________________________ > LLVM Developers ma...

...there are more back-ends having '[]'-patterns). > [Villmow, Micah] Have you tried using a tablegen pattern here? I find it is easier for simple conversions like this than using C++ code. > For example our backend does this with: > def uitoli64rr:Pat < (i64 (zext GPRI32:$src)), (LCREATEi64rr GPRI32:$src, (LOADCONSTi32 0)) >; > Where LCREATE is a machine instruction that does similar to ISD::BUILD_PAIR from two i32's and outputs a i64. > I already tried to use a pattern, but for some reason I messed it up. Giving it another try now, I finally succeeded :-) And yes, i...

Hi LLVM-Folks, as mentioned in an earlier post (http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I am currently working on a Back-End for the TriCore processor. Currently, I am struggling as LLVM could not select zext and load, for instance, so some of the testcases in test/CodeGen/Generic are not successfully compiled by my back-end. Furthermore, I am completely puzzled by the

...el time, they have no pattern. > > > [Villmow, Micah] Have you tried using a tablegen pattern here? I find > it is easier for simple conversions like this than using C++ code. > > For example our backend does this with: > > def uitoli64rr:Pat < (i64 (zext GPRI32:$src)), (LCREATEi64rr > > GPRI32:$src, (LOADCONSTi32 0)) >; Where LCREATE is a machine > instruction that does similar to ISD::BUILD_PAIR from two i32's and > outputs a i64. > > > > I already tried to use a pattern, but for some reason I messed it up. > Giving it another try now,...