Displaying 3 results from an estimated 3 matches for "lcpi4_2".
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lcpi0_2
2019 Mar 28
3
Why does LLVM keep some loads in the loops even after applying the O3 optimization?
...vldr s0, [r0]
mov r0, r6
vcvt.f64.f32 d0, s0
vmov r2, r3, d0
bl fprintf
cmp r0, #0
blt .LBB4_25
@ BB#20: @ %for.cond.89
@ in Loop: Header=BB4_19 Depth=1
ldr r0, .LCPI4_2
add r4, r4, #1
add r7, r7, #4
ldr r0, [r0]
cmp r4, r0
blt .LBB4_19
There are no other basic blocks in the loop. I am wondering why the first
load instruction (ldr r0, [r5]) is repeatedly executed in the loop while
the load address (r5) is never changed in t...
2019 Mar 28
2
Why does LLVM keep some loads in the loops even after applying the O3 optimization?
...vcvt.f64.f32 d0, s0
> vmov r2, r3, d0
> bl fprintf
> cmp r0, #0
> blt .LBB4_25
> @ BB#20: @ %for.cond.89
> @ in Loop: Header=BB4_19 Depth=1
> ldr r0, .LCPI4_2
> add r4, r4, #1
> add r7, r7, #4
> ldr r0, [r0]
> cmp r4, r0
> blt .LBB4_19
>
> There are no other basic blocks in the loop. I am wondering why the first load instruction (ldr r0, [r5]) is repeatedly executed in the loop whi...
2012 Apr 03
1
[LLVMdev] pb05 results for current llvm/dragonegg
Attached are the Polyhedron 2005 benchmark results for current llvm/dragonegg svn
on x86_64-apple-darwin11 built against Xcode 4.3.2 and FSF gcc 4.6.3. The benchmarks
for -msse3 and -msse4 appear identical (at least for degg+optnz). This is fortunate
since there seems to be a bug in -msse4 on 2.33 GHz (T7600) Intel Core 2 Duo Merom
(http://llvm.org/bugs/show_bug.cgi?id=12434). I've added two