search for: lcpi1_2

...3, 0($3) bltz $3, $BB0_1 nop # BB#2: The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM backend, .LBB1_1: ldr r2, .LCPI1_2 ldr r2, [r2] cmp r2, #0 blt .LBB1_1 @ BB#2: The first ldr instruction is to load the address from constant pool. It also should be outside the loop. I'm not sure if this is because of the optimisations are not enough in the common SelectionDAG optimisation phase, or should this kind of...

...gt; > The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM backend, > > .LBB1_1: > ldr r2, .LCPI1_2 > ldr r2, [r2] > cmp r2, #0 > blt .LBB1_1 > @ BB#2: > > The first ldr instruction is to load the address from constant pool. It also should be outside the loop. > > I'm not sure if this is because of the optimisations are not enough in the common SelectionDAG op...

...t;> >> The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM backend, >> >> .LBB1_1: >> ldr r2, .LCPI1_2 >> ldr r2, [r2] >> cmp r2, #0 >> blt .LBB1_1 >> @ BB#2: >> >> The first ldr instruction is to load the address from constant pool. It also should be outside the loop. >> >> I'm not sure if this is because of the optimisations are not enou...