Displaying 10 results from an estimated 10 matches for "lcpi1_1".
Did you mean:
lcpi1_0
2011 Apr 27
2
[LLVMdev] built-in longjmp and setjmp
...i2.
According to the standard, shouldn't ++gi2 be executed twice regardless of
whether gi2 is volatile or not? Isn't the missing chain from EH_SJLJ_SETJMP
node to load/store nodes that access gi2 causing this problem (please see
attached file in my previous email)?
# line 39 - 47
ldr r1, LCPI1_1
ldr r2, [r1]
add r2, r2, #1
str r2, [r1]
add r4, pc, #8 @ eh_setjmp begin
str r4, [r0, #4]
mov r0, #0
add pc, pc, #0
mov r0, #1 @ eh_setjmp end
...
LCPI1_1:
.long _gi2
.align 2
On Wed, Apr 27, 2011 at 11:38 AM, Akira Hatanaka <ahatanak at gmail.com&...
2011 Apr 27
3
[LLVMdev] built-in longjmp and setjmp
...t ++gi2 be executed twice regardless
> of whether gi2 is volatile or not? Isn't the missing chain from
> EH_SJLJ_SETJMP node to load/store nodes that access gi2 causing this problem
> (please see attached file in my previous email)?
> >
> > # line 39 - 47
> > ldr r1, LCPI1_1
> > ldr r2, [r1]
> > add r2, r2, #1
> > str r2, [r1]
> > add r4, pc, #8 @ eh_setjmp begin
> > str r4, [r0, #4]
> > mov r0, #0
> > add pc, pc, #0
> > mov r0, #1 @ eh_setjmp end
> >
> > ...
> > LC...
2011 Apr 27
0
[LLVMdev] built-in longjmp and setjmp
...o the standard, shouldn't ++gi2 be executed twice regardless of whether gi2 is volatile or not? Isn't the missing chain from EH_SJLJ_SETJMP node to load/store nodes that access gi2 causing this problem (please see attached file in my previous email)?
>
> # line 39 - 47
> ldr r1, LCPI1_1
> ldr r2, [r1]
> add r2, r2, #1
> str r2, [r1]
> add r4, pc, #8 @ eh_setjmp begin
> str r4, [r0, #4]
> mov r0, #0
> add pc, pc, #0
> mov r0, #1 @ eh_setjmp end
>
> ...
> LCPI1_1:
> .long _gi2
> .align 2
>
>...
2011 Apr 27
0
[LLVMdev] built-in longjmp and setjmp
...d, shouldn't ++gi2 be executed twice regardless of whether gi2 is volatile or not? Isn't the missing chain from EH_SJLJ_SETJMP node to load/store nodes that access gi2 causing this problem (please see attached file in my previous email)?
> >
> > # line 39 - 47
> > ldr r1, LCPI1_1
> > ldr r2, [r1]
> > add r2, r2, #1
> > str r2, [r1]
> > add r4, pc, #8 @ eh_setjmp begin
> > str r4, [r0, #4]
> > mov r0, #0
> > add pc, pc, #0
> > mov r0, #1 @ eh_setjmp end
> >
> > ...
> > LC...
2011 Apr 27
1
[LLVMdev] built-in longjmp and setjmp
...uted twice regardless
> of whether gi2 is volatile or not? Isn't the missing chain from
> EH_SJLJ_SETJMP node to load/store nodes that access gi2 causing this problem
> (please see attached file in my previous email)?
> > >
> > > # line 39 - 47
> > > ldr r1, LCPI1_1
> > > ldr r2, [r1]
> > > add r2, r2, #1
> > > str r2, [r1]
> > > add r4, pc, #8 @ eh_setjmp begin
> > > str r4, [r0, #4]
> > > mov r0, #0
> > > add pc, pc, #0
> > > mov r0, #1 @ eh_setjmp e...
2013 Jan 23
2
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
...bge .LBB1_3
> and r4, r3, r12 # mask with 0xffff to convert to short again
> lsl r4, r4, #16 # this lsl and the following
> asr r5, r4, #16 # asr implement sign-extension to 32 bits again ....
> ldr r4, .LCPI1_1
> cmn r5, #2048
> movge r4, r3
> .LBB1_3:
> str r4, [r2, r0, lsl #2]
> add r0, r0, #1
> add r1, r1, #2
> cmp r0, #67
> blt .LBB1_1
>
> Clearly the sign-extensions...
2011 Apr 27
0
[LLVMdev] built-in longjmp and setjmp
I have another basic question about setjmp/longjmp.
When I compile and run the following program, is it expected that global
variable gi2 will be incremented twice? It seems that the code generated
with clang and llc increments it only once (line 37-43 of attached file).
$ clang setjmp6.c -o setjmp6.arm.ll -emit-llvm -O3 -S -ccc-host-triple
arm-unknown-darwin -ccc-clang-archs arm
$ llc
2011 Apr 13
3
[LLVMdev] built-in longjmp and setjmp
On Apr 13, 2011, at 9:51 AM, Akira Hatanaka wrote:
> int
> main (int argc, char** argv)
> {
> int n = atoi(argv[1]), r;
>
> if ((r = setjmp (buf)))
> {
> printf("n = %d\n", n);
> return 0;
> }
Non-volatile local variables are not preserved by setjmp(), so this program can print whatever it wants.
/jakob
2013 Jan 24
0
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
....LBB1_3
>> and r4, r3, r12 # mask with 0xffff to convert to short again
>> lsl r4, r4, #16 # this lsl and the following
>> asr r5, r4, #16 # asr implement sign-extension to 32 bits again ....
>> ldr r4, .LCPI1_1
>> cmn r5, #2048
>> movge r4, r3
>> .LBB1_3:
>> str r4, [r2, r0, lsl #2]
>> add r0, r0, #1
>> add r1, r1, #2
>> cmp r0, #67
>> blt .LBB1_1
>>
>...
2013 Jan 21
3
[LLVMdev] introducing sign extending halfword loads into the LLVM IR
On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
> On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote:
>
>> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are