search for: lbrs

...; + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0); > + if (lbr_stack.lbr_info) > + add_atomic_switch_msr(vmx, lbr_stack.lbr_info + i, 0, > + 0); > + } That will be really expensive and add a lot of overhead to every entry/exit. perf can already context switch the LBRs on task context switch. With that you can just switch LBR_SELECT, which is *much* cheaper because there are far less context switches than exit/entries. It implies that when KVM is running it needs to prevent perf from enabling LBRs in the context of KVM, but that should be straight forward. -And...

...; + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0); > + if (lbr_stack.lbr_info) > + add_atomic_switch_msr(vmx, lbr_stack.lbr_info + i, 0, > + 0); > + } That will be really expensive and add a lot of overhead to every entry/exit. perf can already context switch the LBRs on task context switch. With that you can just switch LBR_SELECT, which is *much* cheaper because there are far less context switches than exit/entries. It implies that when KVM is running it needs to prevent perf from enabling LBRs in the context of KVM, but that should be straight forward. -And...

...r(vmx, lbr_stack.lbr_to + i, 0, 0); >> + if (lbr_stack.lbr_info) >> + add_atomic_switch_msr(vmx, lbr_stack.lbr_info + i, 0, >> + 0); >> + } > That will be really expensive and add a lot of overhead to every entry/exit. > perf can already context switch the LBRs on task context switch. With that > you can just switch LBR_SELECT, which is *much* cheaper because there > are far less context switches than exit/entries. > > It implies that when KVM is running it needs to prevent perf from enabling > LBRs in the context of KVM, but that should be...

...a normal perf PMI does at least 1 MSR reads and 4+ MSR writes for a single counter. With multiple counters it gets worse. For each of those you'll need to exit. Adding something to the entry/exit list is similar to the cost of doing explicit RD/WRMSRs. On Skylake we have 32*3=96 MSRs for the LBRs. So with the 5 exits and entries, you're essentually doing 5*2*96=18432 extra MSR accesses for each PMI. MSR access is 100+ cycles at least, for writes it is far more expensive. -Andi

...a normal perf PMI does at least 1 MSR reads and 4+ MSR writes for a single counter. With multiple counters it gets worse. For each of those you'll need to exit. Adding something to the entry/exit list is similar to the cost of doing explicit RD/WRMSRs. On Skylake we have 32*3=96 MSRs for the LBRs. So with the 5 exits and entries, you're essentually doing 5*2*96=18432 extra MSR accesses for each PMI. MSR access is 100+ cycles at least, for writes it is far more expensive. -Andi

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch

...00000000000040 13=0000000000000000 R14=00000000772CCDD8 15=000000006BBC566F SI=000000006BBC55B0 DI=000000006BBC55B0 CR2=0000000000000000 CR3=000000006BB25000 CR0=80000013 CR4=00000668 CR8=00000000 CS=0038 DS=0038 SS=0030 ES=0038 RFLAGS=00010A07 MSR1D9=4801 345=32C4 1C9=0003 LBRs From To From To From To From To 01h 00093009->746EC191 7846C3B4->0005E598 7846C39A->7846C3B4 7846E2B5->7846C392 05h 746ECBEB->7846E290 0005E598->746ECBE0 7846C3B4->00000BC4 7846C39A->7846C3B4 09h 7846E2B5->7846C3...